void __init dm365_init_vc(struct snd_platform_data *pdata) { davinci_cfg_reg(DM365_EVT2_VC_TX); davinci_cfg_reg(DM365_EVT3_VC_RX); dm365_vc_device.dev.platform_data = pdata; platform_device_register(&dm365_vc_device); }
int set_tsif_clk(enum tsif_clk_speed clk_speed) { unsigned int value; unsigned int sys_vddpwdn = (unsigned int)IO_ADDRESS(0x01C40048); unsigned int sys_tsif_ctl = (unsigned int)IO_ADDRESS(0x01C40050); unsigned int sys_vsclkdis = (unsigned int)IO_ADDRESS(0x01C4006C); davinci_cfg_reg(DM646X_CRGMUX); davinci_cfg_reg(DM646X_STSOMUX); davinci_cfg_reg(DM646X_STSIMUX); { int err = 0; char val2[2]; val2[0] = 0x27 | 0x80; val2[1] = tsif_output_clk_freq[clk_speed][0]; err = davinci_i2c_write(2, val2, CDCE949); val2[0] = 0x28 | 0x80; val2[1] = tsif_output_clk_freq[clk_speed][1]; err = davinci_i2c_write(2, val2, CDCE949); val2[0] = 0x29 | 0x80; val2[1] = tsif_output_clk_freq[clk_speed][2]; err = davinci_i2c_write(2, val2, CDCE949); val2[0] = 0x2a | 0x80; val2[1] = tsif_output_clk_freq[clk_speed][3]; err = davinci_i2c_write(2, val2, CDCE949); val2[0] = 0x2b | 0x80; val2[1] = tsif_output_clk_freq[clk_speed][4]; err = davinci_i2c_write(2, val2, CDCE949); val2[0] = 0x24 | 0x80; val2[1] = 0x6f; err = davinci_i2c_write(2, val2, CDCE949); } mdelay(200); value = 2 << 12 | /* Auxclk */ 8 << 8 | /* CRG0_VCXI */ 2 << 4 | /* Auxclk */ 0; /* CRG0_VCXI */ outl(value, sys_tsif_ctl); /* Enable all the TSIF related clocks */ value = inl(sys_vsclkdis); value &= ~(unsigned int)(0x000000FC); outl(value, sys_vsclkdis); /* Powerup UART1 Flow control and Data */ value = inl(sys_vddpwdn); value &= ~(unsigned int)(0x000000C0); outl(value, sys_vddpwdn); return 0; }
void dm646x_setup_vpif(struct vpif_display_config *display_config, struct vpif_capture_config *capture_config) { unsigned int value; void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE); value = __raw_readl(base + VSCLKDIS_OFFSET); value &= ~VSCLKDIS_MASK; __raw_writel(value, base + VSCLKDIS_OFFSET); value = __raw_readl(base + VDD3P3V_PWDN_OFFSET); value &= ~VDD3P3V_VID_MASK; __raw_writel(value, base + VDD3P3V_PWDN_OFFSET); davinci_cfg_reg(DM646X_STSOMUX_DISABLE); davinci_cfg_reg(DM646X_STSIMUX_DISABLE); davinci_cfg_reg(DM646X_PTSOMUX_DISABLE); davinci_cfg_reg(DM646X_PTSIMUX_DISABLE); if (cpu_is_davinci_dm646x_v30()) { display_config->ch2_clip_en = true; display_config->ch3_clip_en = true; } vpif_display_dev.dev.platform_data = display_config; vpif_capture_dev.dev.platform_data = capture_config; platform_device_register(&vpif_dev); platform_device_register(&vpif_display_dev); platform_device_register(&vpif_capture_dev); }
static int spi_gpio_open(struct inode *inode, struct file *filp) { davinci_cfg_reg(DM365_GPIO35, PINMUX_RESV); davinci_cfg_reg(DM365_GPIO36, PINMUX_RESV); davinci_cfg_reg(DM365_GPIO37, PINMUX_RESV); printk("zhoujian@@@spi_gpio_open \n"); return 0; }
static void dm365_isif_setup_pinmux(void) { davinci_cfg_reg(DM365_VIN_CAM_WEN); davinci_cfg_reg(DM365_VIN_CAM_VD); davinci_cfg_reg(DM365_VIN_CAM_HD); davinci_cfg_reg(DM365_VIN_YIN4_7_EN); davinci_cfg_reg(DM365_VIN_YIN0_3_EN); }
static int spi_gpio_release(struct inode *inode, struct file *filp) { davinci_cfg_reg(DM365_GPIO35, PINMUX_FREE); davinci_cfg_reg(DM365_GPIO36, PINMUX_FREE); davinci_cfg_reg(DM365_GPIO37, PINMUX_FREE); printk("zhoujian@@@spi_gpio_release \n"); return 0; }
static inline void da850_evm_setup_nor_nand(void) { int ret = 0; if (ui_card_detected && !HAS_MMC) { ret = davinci_cfg_reg_list(da850_evm_nand_pins); if (ret) pr_warning("da850_evm_init: nand mux setup failed: " "%d\n", ret); ret = davinci_cfg_reg(DA850_GPIO0_11); if (ret) pr_warning("da850_evm_init:GPIO(0,11) mux setup " "failed\n"); ret = gpio_request(DA850_SD_ENABLE_PIN, "mmc_sd_en"); if (ret) pr_warning("Cannot open GPIO %d\n", DA850_SD_ENABLE_PIN); /* Driver GP0[11] low for NOR to work */ gpio_direction_output(DA850_SD_ENABLE_PIN, 0); ret = davinci_cfg_reg_list(da850_evm_nor_pins); if (ret) pr_warning("da850_evm_init: nor mux setup failed: %d\n", ret); platform_add_devices(da850_evm_devices, ARRAY_SIZE(da850_evm_devices)); } else if (ui_card_detected && HAS_MMC) { /* * On Logic PD Rev.3 EVMs GP0[11] pin needs to be configured * for MMC and NOR to work. When GP0[11] is low, the SD0 * interface will not work, but NOR flash will. When GP0[11] * is high, SD0 will work but NOR flash will not. By default * we are assuming that GP0[11] pin is driven high, when UI * card is not connected. Hence we are not configuring the * GP0[11] pin when MMC/SD is enabled and UI card is not * connected. Not configuring the GPIO pin will enable the * bluetooth to work on AM18x as it requires the GP0[11] * pin for UART flow control. */ ret = davinci_cfg_reg(DA850_GPIO0_11); if (ret) pr_warning("da850_evm_init:GPIO(0,11) mux setup " "failed\n"); ret = gpio_request(DA850_SD_ENABLE_PIN, "mmc_sd_en"); if (ret) pr_warning("Cannot open GPIO %d\n", DA850_SD_ENABLE_PIN); /* Driver GP0[11] high for SD to work */ gpio_direction_output(DA850_SD_ENABLE_PIN, 1); } }
static int __init r61505w_probe(struct spi_device *spi) { int ret; spi->bits_per_word = 24; ret = spi_setup(spi); g_spi = spi; printk("zhoujian@@r61505w_probe\n\r"); davinci_cfg_reg(DM365_GPIO35, PINMUX_RESV); davinci_cfg_reg(DM365_GPIO36, PINMUX_RESV); davinci_cfg_reg(DM365_GPIO37, PINMUX_RESV); gpio_direction_output(SPI_GPIO_SCL, 1); gpio_direction_output(SPI_GPIO_SDI, 1); // gpio_direction_output(SPI_GPIO_SDO, 1); gpio_direction_output(SPI_GPIO_CS, 1); r61505w_ldi_init(); // r61505w_ldi_enable(); r61505w_updata_backlight(BL_LEVEL3); davinci_cfg_reg(DM365_GPIO35, PINMUX_FREE); davinci_cfg_reg(DM365_GPIO36, PINMUX_FREE); davinci_cfg_reg(DM365_GPIO37, PINMUX_FREE); davinci_cfg_reg(DM365_SPI4_SCLK, PINMUX_RESV); davinci_cfg_reg(DM365_SPI4_SDO, PINMUX_RESV); davinci_cfg_reg(DM365_SPI4_SDENA0, PINMUX_RESV); if (ret < 0) return 0; return ret; }
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata) { /* we don't use ASP1 IRQs, or we'd need to mux them ... */ if (evt_enable & ASP1_TX_EVT_EN) davinci_cfg_reg(DM355_EVT8_ASP1_TX); if (evt_enable & ASP1_RX_EVT_EN) davinci_cfg_reg(DM355_EVT9_ASP1_RX); dm355_asp1_device.dev.platform_data = pdata; platform_device_register(&dm355_asp1_device); }
static void __init evm_init_i2c(void) { davinci_cfg_reg(DM365_I2C_SDA); davinci_cfg_reg(DM365_I2C_SCL); davinci_init_i2c(&i2c_pdata); //if (have_imager()) // i2c_add_driver(&pca9543a_driver); if( LENA_GROUND == device_lena_air_id ) { i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); } }
static int dm644x_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, int field) { int ret = 0; switch (if_type) { case V4L2_MBUS_FMT_SGRBG8_1X8: /* * This was VPBE_DIGITAL_IF_PRGB. Replace the enum accordingly * when the right one gets into open source */ davinci_cfg_reg(DM644X_GPIO46_47); davinci_cfg_reg(DM644X_GPIO0); davinci_cfg_reg(DM644X_RGB666); davinci_cfg_reg(DM644X_LOEEN); davinci_cfg_reg(DM644X_GPIO3); break; case V4L2_MBUS_FMT_YUYV10_1X20: /* * This was VPBE_DIGITAL_IF_YCC16. Replace the enum accordingly * when the right one gets into open source */ if (field) davinci_cfg_reg(DM644X_LFLDEN); else davinci_cfg_reg(DM644X_GPIO3); davinci_cfg_reg(DM644X_LOEEN); break; default: ret = -EINVAL; } return ret; }
/* Connect the I2C pins to the I2C controller. */ static void enable_i2c_pins(void) { unsigned long flags; local_irq_save(flags); if (cpu_is_davinci_dm644x()) davinci_cfg_reg(DM644X_I2C); else if (cpu_is_davinci_dm355()) { davinci_cfg_reg(DM355_I2C_SDA); davinci_cfg_reg(DM355_I2C_SCL); } local_irq_restore(flags); }
static __init void davinci_sffsdr_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; platform_add_devices(davinci_sffsdr_devices, ARRAY_SIZE(davinci_sffsdr_devices)); sffsdr_init_i2c(); davinci_serial_init(&uart_config); soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; davinci_setup_usb(0, 0); /* We support only peripheral mode. */ /* mux VLYNQ pins */ davinci_cfg_reg(DM644X_VLYNQEN); davinci_cfg_reg(DM644X_VLYNQWD); }
/* Om DM365, Imager and TVP5146 I2C address collide. So we need to * keep imager on reset when working with tvp5146 and vice-versa * This function use GIO40 to act as reset to imager */ void image_sensor_hw_reset(int state) { u32 val1; if (cpu_is_davinci_dm365()) { val1 = cpld_read(DM365_CPLD_REGISTER3); val1 |= DM365_IMAGER_RST_MASK; cpld_write(val1, DM365_CPLD_REGISTER3); /* CPLD to Route GPIO to Imager Reset line */ val1 = cpld_read(DM365_CPLD_REGISTER16); val1 &= ~0x40404040; cpld_write(val1, DM365_CPLD_REGISTER16); val1 = cpld_read(DM365_CPLD_REGISTER18); val1 |= 0x20202020; cpld_write(val1, DM365_CPLD_REGISTER18); val1 = cpld_read(DM365_CPLD_REGISTER18); val1 &= ~0x01010101; cpld_write(val1, DM365_CPLD_REGISTER18); #ifndef CONFIG_MTD_CFI /* When NOR flash is use and at 16-bit access mode. GPIO 40 is used as address bus */ /* Pin mux to use GPIO40 */ davinci_cfg_reg(DM365_GPIO40, PINMUX_RESV); /* Configure GPIO40 to be output and hight */ if (state) gpio_direction_output(40, 1); else gpio_direction_output(40, 0); #endif } }
static int led_off(void) { int ret; /*Free gpio */ gpio_free(PIN_LED); /*Configure in mux.h */ ret = davinci_cfg_reg (MUX_LED); if (ret<0) { printk(KERN_INFO "No es posible configurar el led 1\n"); return ret; } /*Configure as out put */ ret = gpio_request(PIN_LED, "led"); if (ret) { printk(KERN_INFO "No es posible configurar el led 2\n"); return ret; } /*Configure as out put */ gpio_direction_output(PIN_LED, 1); /*TURN OFF */ gpio_set_value(PIN_LED, 0); return 0 ; }
static void dm365evm_usb_configure(void) { davinci_cfg_reg(DM365_GPIO33); gpio_request(33, "usb"); gpio_direction_output(33, 1); setup_usb(500, 8); }
/** * dm365evm_reset_imager() - reset the image sensor * @en: enable/disable flag */ static void dm365evm_reset_imager(int rst) { u8 val; val = __raw_readb(cpld + CPLD_POWER) | BIT(3) | BIT(11) | BIT(19) | BIT(27); __raw_writeb(val, (cpld + CPLD_POWER)); val = __raw_readb(cpld + CPLD_MUX) | BIT(6) | BIT(14) | BIT(22) | BIT(30); __raw_writeb(val, (cpld + CPLD_MUX)); /* Reset bit6 of CPLD_IMG_DIR2 */ val = __raw_readb(cpld + CPLD_IMG_DIR2) & ~BIT(6); __raw_writeb(val, (cpld + CPLD_IMG_DIR2)); /* Set bit5 of CPLD_IMG_MUX5 */ val = __raw_readb(cpld + CPLD_IMG_MUX5) | BIT(5); __raw_writeb(val, (cpld + CPLD_IMG_MUX5)); /* Reset bit 0 of CPLD_IMG_MUX5 */ val = __raw_readb(cpld + CPLD_IMG_MUX5) & ~BIT(0); __raw_writeb(val, (cpld + CPLD_IMG_MUX5)); /** * Configure GPIO40 to be output and high. This has dependency on MMC1 */ davinci_cfg_reg(DM365_GPIO40); gpio_request(40, "sensor_reset"); if (rst) gpio_direction_output(40, 1); else gpio_direction_output(40, 0); }
static int __init dm365_init_devices(void) { if (!cpu_is_davinci_dm365()) return 0; davinci_cfg_reg(DM365_INT_EDMA_CC); platform_device_register(&dm365_edma_device); platform_device_register(&dm365_emac_device); /* * setup Mux configuration for vpfe input and register * vpfe capture platform device */ platform_device_register(&dm365_vpss_device); platform_device_register(&dm365_ipipeif_dev); platform_device_register(&dm365_isif_dev); platform_device_register(&vpfe_capture_dev); /* Register OSD device */ platform_device_register(&dm365_osd_dev); /* Register VENC device */ platform_device_register(&dm365_venc_dev); return 0; }
void __init davinci_init_ide(void) { if (cpu_is_davinci_dm644x()) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN); davinci_cfg_reg(DM644X_HDIREN); } else if (cpu_is_davinci_dm646x()) { /* IRQ_DM646X_IDE is the same as IRQ_IDE */ davinci_cfg_reg(DM646X_ATAEN); } else { WARN_ON(1); return; } platform_device_register(&ide_device); }
void __init dm355_init_spi0(unsigned chipselect_mask, const struct spi_board_info *info, unsigned len) { /* for now, assume we need MISO */ davinci_cfg_reg(DM355_SPI0_SDI); /* not all slaves will be wired up */ if (chipselect_mask & BIT(0)) davinci_cfg_reg(DM355_SPI0_SDENA0); if (chipselect_mask & BIT(1)) davinci_cfg_reg(DM355_SPI0_SDENA1); spi_register_board_info(info, len); platform_device_register(&dm355_spi0_device); }
static int __init da850_evm_config_emac(void) { void __iomem *cfg_chip3_base; int ret; u32 val; struct davinci_soc_info *soc_info = &davinci_soc_info; u8 rmii_en = soc_info->emac_pdata->rmii_en; if (!machine_is_davinci_da850_evm()) return 0; cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); val = __raw_readl(cfg_chip3_base); if (rmii_en) { val |= BIT(8); ret = davinci_cfg_reg_list(da850_rmii_pins); pr_info("EMAC: RMII PHY configured, MII PHY will not be" " functional\n"); } else { val &= ~BIT(8); ret = davinci_cfg_reg_list(da850_cpgmac_pins); pr_info("EMAC: MII PHY configured, RMII PHY will not be" " functional\n"); } if (ret) pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n", ret); /* configure the CFGCHIP3 register for RMII or MII */ __raw_writel(val, cfg_chip3_base); ret = davinci_cfg_reg(DA850_GPIO2_6); if (ret) pr_warning("da850_evm_init:GPIO(2,6) mux setup " "failed\n"); ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en"); if (ret) { pr_warning("Cannot open GPIO %d\n", DA850_MII_MDIO_CLKEN_PIN); return ret; } /* Enable/Disable MII MDIO clock */ gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en); soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY; ret = da8xx_register_emac(); if (ret) pr_warning("da850_evm_init: emac registration failed: %d\n", ret); return 0; }
void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata) { if (cpu_is_davinci_dm644x()) davinci_cfg_reg(DM644X_I2C); davinci_i2c_device.dev.platform_data = pdata; (void) platform_device_register(&davinci_i2c_device); }
void __init dm365_init_spi0(unsigned chipselect_mask, struct spi_board_info *info, unsigned len) { davinci_cfg_reg(DM365_SPI0_SCLK); davinci_cfg_reg(DM365_SPI0_SDI); davinci_cfg_reg(DM365_SPI0_SDO); /* not all slaves will be wired up */ if (chipselect_mask & BIT(0)) davinci_cfg_reg(DM365_SPI0_SDENA0); if (chipselect_mask & BIT(1)) davinci_cfg_reg(DM365_SPI0_SDENA1); spi_register_board_info(info, len); platform_device_register(&dm365_spi0_device); }
static int __init tsif_control_init(void) { struct platform_device *pldev; int result, ret = 0; dev_t devno; unsigned int size = 0, mem_size, i, j; set_tsif_clk(TSIF_16_875_MHZ_SERIAL_PARALLEL); davinci_cfg_reg(DM646X_PTSOMUX_PARALLEL); davinci_cfg_reg(DM646X_PTSIMUX_PARALLEL); size = tsif_device_count * tsif_control_minor_count; /* Register the driver in the kernel */ result = alloc_chrdev_region(&devno, 0, size, DRIVER_NAME); if (result < 0) { printk(KERN_ERR "TSIF: Module intialization failed.\ could not register character device\n"); return -ENODEV; }
static int __init dm355_init_devices(void) { if (!cpu_is_davinci_dm355()) return 0; davinci_cfg_reg(DM355_INT_EDMA_CC); platform_device_register(&dm355_edma_device); return 0; }
static __init void davinci_ntosd2_init(void) { struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; int status; aemif_clk = clk_get(NULL, "aemif"); clk_enable(aemif_clk); if (HAS_ATA) { if (HAS_NAND) pr_warning("WARNING: both IDE and Flash are " "enabled, but they share AEMIF pins.\n" "\tDisable IDE for NAND/NOR support.\n"); davinci_init_ide(); } else if (HAS_NAND) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN_DISABLE); /* only one device will be jumpered and detected */ if (HAS_NAND) platform_device_register( &davinci_ntosd2_nandflash_device); } platform_add_devices(davinci_ntosd2_devices, ARRAY_SIZE(davinci_ntosd2_devices)); /* Initialize I2C interface specific for this board */ status = ntosd2_init_i2c(); if (status < 0) pr_warning("davinci_ntosd2_init: msp430 irq setup failed:" " %d\n", status); davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_ntosd2_snd_data); soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY; davinci_setup_usb(1000, 8); /* * Mux the pins to be GPIOs, VLYNQEN is already done at startup. * The AEAWx are five new AEAW pins that can be muxed by separately. * They are a bitmask for GPIO management. According TI * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ * gpio(10,11,12,13) for leds any combination of bits works except * four last. So we are to reset all five. */ davinci_cfg_reg(DM644X_AEAW0); davinci_cfg_reg(DM644X_AEAW1); davinci_cfg_reg(DM644X_AEAW2); davinci_cfg_reg(DM644X_AEAW3); davinci_cfg_reg(DM644X_AEAW4); davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); }
void __init dm365_init_asp(struct snd_platform_data *pdata) { davinci_cfg_reg(DM365_MCBSP0_BDX); davinci_cfg_reg(DM365_MCBSP0_X); davinci_cfg_reg(DM365_MCBSP0_BFSX); davinci_cfg_reg(DM365_MCBSP0_BDR); davinci_cfg_reg(DM365_MCBSP0_R); davinci_cfg_reg(DM365_MCBSP0_BFSR); davinci_cfg_reg(DM365_EVT2_ASP_TX); davinci_cfg_reg(DM365_EVT3_ASP_RX); dm365_asp_device.dev.platform_data = pdata; platform_device_register(&dm365_asp_device); }
static void dm355_ccdc_setup_pinmux(void) { davinci_cfg_reg(DM355_VIN_PCLK); davinci_cfg_reg(DM355_VIN_CAM_WEN); davinci_cfg_reg(DM355_VIN_CAM_VD); davinci_cfg_reg(DM355_VIN_CAM_HD); davinci_cfg_reg(DM355_VIN_YIN_EN); davinci_cfg_reg(DM355_VIN_CINL_EN); davinci_cfg_reg(DM355_VIN_CINH_EN); }
int __init_or_module davinci_cfg_reg_list(const short pins[]) { int i, error = -EINVAL; if (pins) for (i = 0; pins[i] >= 0; i++) { error = davinci_cfg_reg(pins[i]); if (error) break; } return error; }
static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type, int field) { switch (if_type) { case V4L2_MBUS_FMT_SGRBG8_1X8: davinci_cfg_reg(DM355_VOUT_FIELD_G70); break; case V4L2_MBUS_FMT_YUYV10_1X20: if (field) davinci_cfg_reg(DM355_VOUT_FIELD); else davinci_cfg_reg(DM355_VOUT_FIELD_G70); break; default: return -EINVAL; } davinci_cfg_reg(DM355_VOUT_COUTL_EN); davinci_cfg_reg(DM355_VOUT_COUTH_EN); return 0; }