/**
* davinci_spi_probe - probe function for SPI Master Controller
* @dev: platform_device structure which contains plateform specific data
*
* According to Linux Deviced Model this function will be invoked by Linux
* with plateform_device struct which contains the device specific info
* like bus_num, num_chipselect (how many slave devices can be connected),
* clock freq. of SPI controller, SPI controller's memory range, IRQ number etc.
* This info will be provided by board specific code which will reside in
* linux-2.6.10/arch/mips/mips-boards/davinci_davinci/davinci_yamuna code.
* This function will map the SPI controller's memory, register IRQ,
* Reset SPI controller and setting its registers to default value.
* It will invoke spi_bitbang_start to create work queue so that client driver
* can register transfer method to work queue.
*/
static int davinci_spi_probe(struct device *d)
{
struct platform_device *dev =
container_of(d, struct platform_device, dev);
struct spi_master *master;
struct davinci_spi *davinci_spi;
struct davinci_spi_platform_data *pdata;
struct resource *r, *mem;
resource_size_t dma_rx_chan, dma_tx_chan, dma_eventq;
int i = 0, ret = 0;
pdata = dev->dev.platform_data;
if (pdata == NULL) {
ret = -ENODEV;
goto err;
}
master = spi_alloc_master(&dev->dev, sizeof(struct davinci_spi));
if (master == NULL) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&dev->dev, master);
davinci_spi = spi_master_get_devdata(master);
if (davinci_spi == NULL) {
ret = -ENOENT;
goto free_master;
}
r = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (r == NULL) {
ret = -ENOENT;
goto free_master;
}
davinci_spi->pbase = r->start;
davinci_spi->region_size = r->end - r->start + 1;
davinci_spi->pdata = pdata;
/* initialize gpio used as chip select */
if (pdata->chip_sel != NULL) {
for (i = 0; i < pdata->num_chipselect; i++) {
if (pdata->chip_sel[i] != DAVINCI_SPI_INTERN_CS)
gpio_direction_output(pdata->chip_sel[i], 1);
}
}
mem = request_mem_region(r->start, davinci_spi->region_size, dev->name);
if (mem == NULL) {
ret = -EBUSY;
goto free_master;
}
davinci_spi->base = (struct davinci_spi_reg __iomem *)
ioremap(r->start, davinci_spi->region_size);
if (davinci_spi->base == NULL) {
ret = -ENOMEM;
goto release_region;
}
davinci_spi->irq = platform_get_irq(dev, 0);
if (davinci_spi->irq <= 0) {
ret = -EINVAL;
goto unmap_io;
}
ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
dev->name, davinci_spi);
if (ret != 0) {
ret = -EAGAIN;
goto unmap_io;
}
/* Allocate tmp_buf for tx_buf */
davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, SLAB_KERNEL);
if (davinci_spi->tmp_buf == NULL) {
ret = -ENOMEM;
goto release_irq;
}
davinci_spi->bitbang.master = spi_master_get(master);
if (davinci_spi->bitbang.master == NULL) {
ret = -ENODEV;
goto free_tmp_buf;
}
if (pdata->clk_name) {
pdata->clk_info = clk_get(d, pdata->clk_name);
if (IS_ERR(pdata->clk_info)) {
ret = -ENODEV;
goto put_master;
}
clk_enable(pdata->clk_info);
} else {
ret = -ENODEV;
goto put_master;
}
master->bus_num = dev->id;
master->num_chipselect = pdata->num_chipselect;
master->setup = davinci_spi_setup;
master->cleanup = davinci_spi_cleanup;
davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
dma_rx_chan = davinci_spi_get_dma_by_flag(dev, IORESOURCE_DMA_RX_CHAN);
dma_tx_chan = davinci_spi_get_dma_by_flag(dev, IORESOURCE_DMA_TX_CHAN);
dma_eventq = davinci_spi_get_dma_by_flag(dev, IORESOURCE_DMA_EVENT_Q);
if (!use_dma ||
dma_rx_chan == DAVINCI_SPI_NO_RESOURCE ||
dma_tx_chan == DAVINCI_SPI_NO_RESOURCE ||
dma_eventq == DAVINCI_SPI_NO_RESOURCE) {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
use_dma = 0;
} else {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
davinci_spi->dma_channels = kzalloc(master->num_chipselect
* sizeof(struct davinci_spi_dma), GFP_KERNEL);
if (davinci_spi->dma_channels == NULL) {
ret = -ENOMEM;
goto free_clk;
}
for (i = 0; i < master->num_chipselect; i++) {
davinci_spi->dma_channels[i].dma_rx_channel = -1;
davinci_spi->dma_channels[i].dma_rx_sync_dev =
dma_rx_chan;
davinci_spi->dma_channels[i].dma_tx_channel = -1;
davinci_spi->dma_channels[i].dma_tx_sync_dev =
dma_tx_chan;
davinci_spi->dma_channels[i].eventq = dma_eventq;
}
}
davinci_spi->version = pdata->version;
davinci_spi->get_rx = davinci_spi_rx_buf_u8;
davinci_spi->get_tx = davinci_spi_tx_buf_u8;
init_completion(&davinci_spi->done);
/* Reset In/OUT SPI modle */
iowrite32(0, davinci_spi->base + SPIGCR0);
udelay(100);
iowrite32(1, davinci_spi->base + SPIGCR0);
ret = spi_bitbang_start(&davinci_spi->bitbang);
if (ret != 0)
goto free_dma;
pr_info("%s: davinci SPI Controller driver at "
"0x%p (irq = %d) use_dma=%d\n",
dev->dev.bus_id, davinci_spi->base, davinci_spi->irq, use_dma);
return ret;
free_dma:
kfree(davinci_spi->dma_channels);
free_clk:
clk_disable(pdata->clk_info);
clk_put(pdata->clk_info);
pdata->clk_info = NULL;
put_master:
spi_master_put(master);
free_tmp_buf:
kfree(davinci_spi->tmp_buf);
release_irq:
free_irq(davinci_spi->irq, davinci_spi);
unmap_io:
iounmap(davinci_spi->base);
release_region:
release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
free_master:
kfree(master);
err:
return ret;
}
/*
* davinci_spi_probe - probe function for SPI Master Controller
* @pdev: platform_device structure which contains plateform specific data
*
* According to Linux Device Model this function will be invoked by Linux
* with plateform_device struct which contains the device specific info.
* This function will map the SPI controller's memory, register IRQ,
* Reset SPI controller and setting its registers to default value.
* It will invoke spi_bitbang_start to create work queue so that client driver
* can register transfer method to work queue.
*/
static int davinci_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct davinci_spi *davinci_spi;
struct davinci_spi_platform_data *pdata;
struct resource *r, *mem;
resource_size_t dma_rx_chan = DAVINCI_SPI_NO_RESOURCE;
resource_size_t dma_tx_chan = DAVINCI_SPI_NO_RESOURCE;
resource_size_t dma_eventq = DAVINCI_SPI_NO_RESOURCE;
int i = 0, ret = 0;
pdata = pdev->dev.platform_data;
if (pdata == NULL) {
ret = -ENODEV;
goto err;
}
master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
if (master == NULL) {
ret = -ENOMEM;
goto err;
}
dev_set_drvdata(&pdev->dev, master);
davinci_spi = spi_master_get_devdata(master);
if (davinci_spi == NULL) {
ret = -ENOENT;
goto free_master;
}
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (r == NULL) {
ret = -ENOENT;
goto free_master;
}
davinci_spi->pbase = r->start;
davinci_spi->region_size = resource_size(r);
davinci_spi->pdata = pdata;
mem = request_mem_region(r->start, davinci_spi->region_size,
pdev->name);
if (mem == NULL) {
ret = -EBUSY;
goto free_master;
}
davinci_spi->base = (struct davinci_spi_reg __iomem *)
ioremap(r->start, davinci_spi->region_size);
if (davinci_spi->base == NULL) {
ret = -ENOMEM;
goto release_region;
}
davinci_spi->irq = platform_get_irq(pdev, 0);
if (davinci_spi->irq <= 0) {
ret = -EINVAL;
goto unmap_io;
}
ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
dev_name(&pdev->dev), davinci_spi);
if (ret != 0) {
ret = -EAGAIN;
goto unmap_io;
}
/* Allocate tmp_buf for tx_buf */
davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
if (davinci_spi->tmp_buf == NULL) {
ret = -ENOMEM;
goto err1;
}
davinci_spi->bitbang.master = spi_master_get(master);
if (davinci_spi->bitbang.master == NULL) {
ret = -ENODEV;
goto free_tmp_buf;
}
davinci_spi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(davinci_spi->clk)) {
ret = -ENODEV;
goto put_master;
}
clk_enable(davinci_spi->clk);
master->bus_num = pdev->id;
master->num_chipselect = pdata->num_chipselect;
master->setup = davinci_spi_setup;
master->cleanup = davinci_spi_cleanup;
davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
davinci_spi->version = pdata->version;
use_dma = pdata->use_dma;
davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
if (davinci_spi->version == SPI_VERSION_2)
davinci_spi->bitbang.flags |= SPI_READY;
if (use_dma) {
dma_rx_chan = davinci_spi_get_dma_by_flag(pdev,
IORESOURCE_DMA_RX_CHAN);
dma_tx_chan = davinci_spi_get_dma_by_flag(pdev,
IORESOURCE_DMA_TX_CHAN);
dma_eventq = davinci_spi_get_dma_by_flag(pdev,
IORESOURCE_DMA_EVENT_Q);
}
if (!use_dma ||
dma_rx_chan == DAVINCI_SPI_NO_RESOURCE ||
dma_tx_chan == DAVINCI_SPI_NO_RESOURCE ||
dma_eventq == DAVINCI_SPI_NO_RESOURCE) {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
use_dma = 0;
} else {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
davinci_spi->dma_channels = kzalloc(master->num_chipselect
* sizeof(struct davinci_spi_dma), GFP_KERNEL);
if (davinci_spi->dma_channels == NULL) {
ret = -ENOMEM;
goto free_clk;
}
for (i = 0; i < master->num_chipselect; i++) {
davinci_spi->dma_channels[i].dma_rx_channel = -1;
davinci_spi->dma_channels[i].dma_rx_sync_dev =
dma_rx_chan;
davinci_spi->dma_channels[i].dma_tx_channel = -1;
davinci_spi->dma_channels[i].dma_tx_sync_dev =
dma_tx_chan;
davinci_spi->dma_channels[i].eventq = dma_eventq;
}
dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
"Using RX channel = %d , TX channel = %d and "
"event queue = %d", dma_rx_chan, dma_tx_chan,
dma_eventq);
}
davinci_spi->get_rx = davinci_spi_rx_buf_u8;
davinci_spi->get_tx = davinci_spi_tx_buf_u8;
init_completion(&davinci_spi->done);
/* Reset In/OUT SPI module */
iowrite32(0, davinci_spi->base + SPIGCR0);
udelay(100);
iowrite32(1, davinci_spi->base + SPIGCR0);
/* Clock internal */
if (davinci_spi->pdata->clk_internal)
set_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
else
clear_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
/* master mode default */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
if (davinci_spi->pdata->intr_level)
iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
else
iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
ret = spi_bitbang_start(&davinci_spi->bitbang);
if (ret != 0)
goto free_clk;
dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
if (!pdata->poll_mode)
dev_info(&pdev->dev, "Operating in interrupt mode"
" using IRQ %d\n", davinci_spi->irq);
return ret;
free_clk:
clk_disable(davinci_spi->clk);
clk_put(davinci_spi->clk);
put_master:
spi_master_put(master);
free_tmp_buf:
kfree(davinci_spi->tmp_buf);
err1:
free_irq(davinci_spi->irq, davinci_spi);
unmap_io:
iounmap(davinci_spi->base);
release_region:
release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
free_master:
kfree(master);
err:
return ret;
}
