/* ** Hardware Single-step Services */ int dbg_hard_stp_event_gp() { ud_t disasm; int rc; if(!dbg_hard_stp_enabled()) return CTRL_EVT_IGNORE; debug(DBG_HARD_STP, "sstep #GP event\n"); dbg_hard_stp_restore_context(); if(!disassemble(&disasm)) return CTRL_EVT_FAIL; rc = __emulate_insn(&disasm); dbg_hard_stp_setup_context(); switch(rc) { case EMU_FAULT: return CTRL_EVT_FAULT; case EMU_UNSUPPORTED: return CTRL_EVT_IGNORE; case EMU_FAIL: return CTRL_EVT_FAIL; } if(disasm.mnemonic == UD_Isysenter) return dbg_hard_stp_event_sysenter(); if(disasm.mnemonic == UD_Isysexit) return dbg_hard_stp_event_sysexit(); return CTRL_EVT_IGNORE; }
static int dbg_hard_stp_event_fast_syscall(int tf) { int rc; dbg_hard_stp_restore_context(); rc = emulate_insn(&info->vm.cpu.disasm); dbg_hard_stp_setup_context(); if(rc == VM_DONE_LET_RIP) { __rflags.tf = tf; __post_access(__rflags); } return rc; }
static int dbg_hard_stp_event_fast_syscall(int tf) { int rc; size_t sz; dbg_hard_stp_restore_context(); sz = ud_insn_len(&info->vm.cpu.disasm); rc = emulate_done(emulate_insn(&info->vm.cpu.disasm), sz); info->vm.cpu.emu_sts = EMU_STS_AVL; /* stealth for db_pending() */ dbg_hard_stp_setup_context(); if(rc == VM_DONE_LET_RIP) { __rflags.tf = tf; __post_access(__rflags); } return rc; }