static boolean_t
rge_factotum_stall_check(rge_t *rgep)
{
uint32_t dogval;
ASSERT(mutex_owned(rgep->genlock));
/*
* Specific check for Tx stall ...
*
* The 'watchdog' counter is incremented whenever a packet
* is queued, reset to 1 when some (but not all) buffers
* are reclaimed, reset to 0 (disabled) when all buffers
* are reclaimed, and shifted left here. If it exceeds the
* threshold value, the chip is assumed to have stalled and
* is put into the ERROR state. The factotum will then reset
* it on the next pass.
*
* All of which should ensure that we don't get into a state
* where packets are left pending indefinitely!
*/
if (rgep->resched_needed)
(void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL);
dogval = rge_atomic_shl32(&rgep->watchdog, 1);
if (dogval < rge_watchdog_count)
return (B_FALSE);
RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval));
return (B_TRUE);
}
static void
rge_wake_factotum(rge_t *rgep)
{
if (rgep->factotum_flag == 0) {
rgep->factotum_flag = 1;
(void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL);
}
}
/**
* High-level Interrupt Service Routine for VMMDev.
*
* This routine simply dispatches a soft-interrupt at an acceptable IPL as
* VGDrvCommonISR() cannot be called at a high IPL (scheduler level or higher)
* due to pollwakeup() in VGDrvNativeISRMousePollEvent().
*
* @param Arg Private data (unused, will be NULL).
* @returns DDI_INTR_CLAIMED if it's our interrupt, DDI_INTR_UNCLAIMED if it isn't.
*/
static uint_t vgdrvSolarisHighLevelISR(caddr_t Arg)
{
bool const fOurIrq = VGDrvCommonIsOurIRQ(&g_DevExt);
if (fOurIrq)
{
ddi_intr_trigger_softint(g_hSoftIntr, NULL /* Arg */);
return DDI_INTR_CLAIMED;
}
return DDI_INTR_UNCLAIMED;
}
void
ddi_trigger_softintr(ddi_softintr_t id)
{
ddi_softint_handle_t *h_p = (ddi_softint_handle_t *)id;
int ret;
if (h_p == NULL)
return;
if ((ret = ddi_intr_trigger_softint(*h_p, NULL)) != DDI_SUCCESS) {
DDI_INTR_APIDBG((CE_CONT, "ddi_trigger_softintr: "
"ddi_intr_trigger_softint failed, hdlp 0x%p "
"ret 0x%x\n", (void *)h_p, ret));
}
}
static void
eib_ctl_comp_intr(ibt_cq_hdl_t cq_hdl, void *arg)
{
eib_vnic_t *vnic = arg;
eib_t *ss = vnic->vn_ss;
eib_chan_t *chan = vnic->vn_ctl_chan;
if (cq_hdl != chan->ch_cq_hdl) {
EIB_DPRINTF_DEBUG(ss->ei_instance, "eib_ctl_comp_intr: "
"cq_hdl(0x%llx) != chan->ch_cq_hdl(0x%llx), "
"ignoring completion", cq_hdl, chan->ch_cq_hdl);
return;
}
ASSERT(vnic->vn_ctl_si_hdl != NULL);
(void) ddi_intr_trigger_softint(vnic->vn_ctl_si_hdl, NULL);
}