int check_ddr_training(void) { #ifdef CONFIG_DDR_TRAINING_STARTUP int ix; char *s = getenv("unddrtr"); if (s && (*s == 'y' || *s == 'Y')) return 0; if (get_ddrtr_result_by_env(&ddrtr_result)) { /* ddr training function will set value to ddr register. */ if (ddr_training()) return 0; setenv(DDR_TRAINING_ENV, dump_ddrtr_result(&ddrtr_result, ' ')); return do_saveenv(NULL, 0, 0, NULL); } printf("Set training value to DDR controller\n"); for (ix = 0; ix < ddrtr_result.count; ix++) { writel(ddrtr_result.reg[ix].val, ddrtr_result.reg[ix].reg); } #endif /* CONFIG_DDR_TRAINING_STARTUP */ return 0; }
int do_ddr_training(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2 || strcmp(argv[1], "training")) { cmd_usage(cmdtp); return 1; } if (ddr_training()) return 0; #ifdef CONFIG_DDR_TRAINING_STARTUP setenv(DDR_TRAINING_ENV, dump_ddrtr_result(&ddrtr_result, ' ')); #endif /* CONFIG_DDR_TRAINING_STARTUP */ return 0; }
void ddr_phy_init(unsigned int mode) { unsigned int timeout = 10000, i; unsigned int mr0_tmp = 1; bool soft_training = false; unsigned int ddr_bl, ddr_cl; dwc_debug("DDR PHY init\n"); ddr_writel(0x150000, DDRP_DTAR); /* DDR training address set*/ ddr_phy_param_init(mode); ddr_chip_init(mode); ddr_training(mode); ddr_impedance_matching(); dwc_debug("DDR PHY init OK\n"); }
int do_ddr_training(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { const char *cmd; if (argc < 2) { cmd_usage(cmdtp); return 1; } cmd = argv[1]; if (!strcmp(cmd, "training")) return ddr_training(); if (!strcmp(cmd, "addrtrain")) return ddr_addrtrain(); if (!strcmp(cmd, "pressure")) return ddrt_pressure(argc - 1, argv + 1); #ifdef CONFIG_DDR_TRAINING_STARTUP setenv(DDR_TRAINING_ENV, dump_ddrtr_result(&ddrtr_result, ' ')); #endif /* CONFIG_DDR_TRAINING_STARTUP */ return 0; }