static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
log_debug("start\n");
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret)
log_debug("Cannot get power supply: ret=%d\n", ret);
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
log_debug("Warning: cannot get enable GPIO: ret=%d\n", ret);
if (ret != -ENOENT)
return log_ret(ret);
}
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
&args);
if (ret) {
log_debug("Cannot get PWM phandle: ret=%d\n", ret);
return log_ret(ret);
}
ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
log_debug("Cannot get PWM: ret=%d\n", ret);
return log_ret(ret);
}
if (args.args_count < 2)
return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
priv->channel = args.args[0];
priv->period_ns = args.args[1];
if (args.args_count > 2)
priv->polarity = args.args[2];
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->levels = malloc(len);
if (!priv->levels)
return log_ret(-ENOMEM);
dev_read_u32_array(dev, "brightness-levels", priv->levels,
count);
priv->num_levels = count;
priv->default_level = priv->levels[index];
priv->max_level = priv->levels[count - 1];
} else {
priv->default_level = index;
priv->max_level = 255;
}
priv->cur_level = priv->default_level;
log_debug("done\n");
return 0;
}
static int vexpress_config_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
struct vexpress_config_sysreg *priv;
const char *prop;
int err, prop_size;
err = dev_read_phandle_with_args(dev, "arm,vexpress,config-bridge",
NULL, 0, 0, &args);
if (err)
return err;
prop = ofnode_get_property(args.node, "compatible", &prop_size);
if (!prop || (strncmp(prop, "arm,vexpress-sysreg", 19) != 0))
return -ENOENT;
priv = calloc(1, sizeof(*priv));
if (!priv)
return -ENOMEM;
dev->uclass_priv = priv;
priv->addr = ofnode_get_addr(args.node);
return dev_read_u32(dev, "arm,vexpress,site", &priv->site);
}
int gpio_request_by_name(struct udevice *dev, const char *list_name, int index,
struct gpio_desc *desc, int flags)
{
struct ofnode_phandle_args args;
int ret;
ret = dev_read_phandle_with_args(dev, list_name, "#gpio-cells", 0,
index, &args);
return gpio_request_tail(ret, dev_ofnode(dev), &args, list_name,
index, desc, flags, index > 0);
}
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
debug("%s: start\n", __func__);
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret)
debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
}
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
&args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
}
priv->channel = args.args[0];
priv->period_ns = args.args[1];
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->default_level = fdt32_to_cpu(cell[index]);
priv->max_level = fdt32_to_cpu(cell[count - 1]);
} else {
priv->default_level = index;
priv->max_level = 255;
}
debug("%s: done\n", __func__);
return 0;
}
static int
pinctrl_gpio_get_pinctrl_and_offset(struct udevice *dev, unsigned offset,
struct udevice **pctldev,
unsigned int *pin_selector)
{
struct ofnode_phandle_args args;
unsigned gpio_offset, pfc_base, pfc_pins;
int ret;
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
0, &args);
if (ret) {
dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
__func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_PINCTRL,
args.node, pctldev);
if (ret) {
dev_dbg(dev,
"%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
gpio_offset = args.args[0];
pfc_base = args.args[1];
pfc_pins = args.args[2];
if (offset < gpio_offset || offset > gpio_offset + pfc_pins) {
dev_dbg(dev,
"%s: GPIO can not be mapped to pincontrol pin\n",
__func__);
return -EINVAL;
}
offset -= gpio_offset;
offset += pfc_base;
*pin_selector = offset;
return 0;
}
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_clk;
struct clk_ops *ops;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
clk->dev = NULL;
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
index, &args);
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
__func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
clk->dev = dev_clk;
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
ret = ops->of_xlate(clk, &args);
else
ret = clk_of_xlate_default(clk, &args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
}
return clk_request(dev_clk, clk);
}
static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
/* Hardcode for now */
priv->phyaddr = -1;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does exist %s\n", dev->name);
priv->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
priv->phy_of_node = phandle_args.node;
priv->max_speed = ofnode_read_u32_default(phandle_args.node,
"max-speed",
SPEED_1000);
}
phy_mode = dev_read_prop(dev, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
return 0;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
struct ofnode_phandle_args args;
u32 *syscfg_base;
u32 mem_remap;
u32 swp_fmc;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
int ret;
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
if (mem_remap != NOT_FOUND) {
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
if (swp_fmc != NOT_FOUND) {
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
}
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
strsep(&bank_name, "@");
if (!bank_name) {
pr_err("missing sdram bank index");
return -EINVAL;
}
bank_params = ¶ms->bank_params[bank];
strict_strtoul(bank_name, 10,
(long unsigned int *)&bank_params->target_bank);
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
pr_err("Found bank %d , but only bank 0 and 1 are supported",
bank_params->target_bank);
return -EINVAL;
}
debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
params->bank_params[bank].sdram_control =
(struct stm32_sdram_control *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-control",
sizeof(struct stm32_sdram_control));
if (!params->bank_params[bank].sdram_control) {
pr_err("st,sdram-control not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
params->bank_params[bank].sdram_timing =
(struct stm32_sdram_timing *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-timing",
sizeof(struct stm32_sdram_timing));
if (!params->bank_params[bank].sdram_timing) {
pr_err("st,sdram-timing not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
bank++;
}
static int gpio_stm32_probe(struct udevice *dev)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct clk clk;
fdt_addr_t addr;
int ret;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
priv->regs = (struct stm32_gpio_regs *)addr;
#ifndef CONFIG_SPL_BUILD
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct ofnode_phandle_args args;
const char *name;
int i;
name = dev_read_string(dev, "st,bank-name");
if (!name)
return -EINVAL;
uc_priv->bank_name = name;
i = 0;
ret = dev_read_phandle_with_args(dev, "gpio-ranges",
NULL, 3, i, &args);
if (ret == -ENOENT) {
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
}
while (ret != -ENOENT) {
priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
args.args[0]);
uc_priv->gpio_count += args.args[2];
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
}
dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
priv->gpio_range);
#endif
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
ret = clk_enable(&clk);
if (ret) {
dev_err(dev, "failed to enable clock\n");
return ret;
}
debug("clock enabled for device %s\n", dev->name);
return 0;
}
