int spi_slave_ofdata_to_platdata(struct udevice *dev,
struct dm_spi_slave_platdata *plat)
{
int mode = 0;
int value;
plat->cs = dev_read_u32_default(dev, "reg", -1);
plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", 0);
if (dev_read_bool(dev, "spi-cpol"))
mode |= SPI_CPOL;
if (dev_read_bool(dev, "spi-cpha"))
mode |= SPI_CPHA;
if (dev_read_bool(dev, "spi-cs-high"))
mode |= SPI_CS_HIGH;
if (dev_read_bool(dev, "spi-3wire"))
mode |= SPI_3WIRE;
if (dev_read_bool(dev, "spi-half-duplex"))
mode |= SPI_PREAMBLE;
/* Device DUAL/QUAD mode */
value = dev_read_u32_default(dev, "spi-tx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
mode |= SPI_TX_DUAL;
break;
case 4:
mode |= SPI_TX_QUAD;
break;
default:
warn_non_spl("spi-tx-bus-width %d not supported\n", value);
break;
}
value = dev_read_u32_default(dev, "spi-rx-bus-width", 1);
switch (value) {
case 1:
break;
case 2:
mode |= SPI_RX_DUAL;
break;
case 4:
mode |= SPI_RX_QUAD;
break;
default:
warn_non_spl("spi-rx-bus-width %d not supported\n", value);
break;
}
plat->mode = mode;
return 0;
}
static int k3_arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
{
struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev);
struct sdhci_host *host = dev_get_priv(dev);
host->name = dev->name;
host->ioaddr = (void *)dev_read_addr(dev);
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
plat->f_max = dev_read_u32_default(dev, "max-frequency", 0);
return 0;
}
static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
pdata->iobase = devfdt_get_addr(dev);
pdata->phy_interface = -1;
phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
return -EINVAL;
}
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
priv->rxdes0_edorr_mask = BIT(30);
priv->txdes0_edotr_mask = BIT(30);
} else {
priv->rxdes0_edorr_mask = BIT(15);
priv->txdes0_edotr_mask = BIT(15);
}
return clk_get_bulk(dev, &priv->clks);
}
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
log_debug("start\n");
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret)
log_debug("Cannot get power supply: ret=%d\n", ret);
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
log_debug("Warning: cannot get enable GPIO: ret=%d\n", ret);
if (ret != -ENOENT)
return log_ret(ret);
}
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
&args);
if (ret) {
log_debug("Cannot get PWM phandle: ret=%d\n", ret);
return log_ret(ret);
}
ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
log_debug("Cannot get PWM: ret=%d\n", ret);
return log_ret(ret);
}
if (args.args_count < 2)
return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
priv->channel = args.args[0];
priv->period_ns = args.args[1];
if (args.args_count > 2)
priv->polarity = args.args[2];
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->levels = malloc(len);
if (!priv->levels)
return log_ret(-ENOMEM);
dev_read_u32_array(dev, "brightness-levels", priv->levels,
count);
priv->num_levels = count;
priv->default_level = priv->levels[index];
priv->max_level = priv->levels[count - 1];
} else {
priv->default_level = index;
priv->max_level = 255;
}
priv->cur_level = priv->default_level;
log_debug("done\n");
return 0;
}
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
{
int err;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
platdata->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("SiFive UART failed to get clock\n");
return err;
}
if (!platdata->clock)
platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
if (!platdata->clock) {
debug("SiFive UART clock not defined\n");
return -EINVAL;
}
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
return 0;
}
static int spi_post_probe(struct udevice *bus)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0);
#endif
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct dm_spi_ops *ops = spi_get_ops(bus);
if (ops->claim_bus)
ops->claim_bus += gd->reloc_off;
if (ops->release_bus)
ops->release_bus += gd->reloc_off;
if (ops->set_wordlen)
ops->set_wordlen += gd->reloc_off;
if (ops->xfer)
ops->xfer += gd->reloc_off;
if (ops->set_speed)
ops->set_speed += gd->reloc_off;
if (ops->set_mode)
ops->set_mode += gd->reloc_off;
if (ops->cs_info)
ops->cs_info += gd->reloc_off;
#endif
return 0;
}
static int fixed_regulator_ofdata_to_platdata(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct fixed_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
int flags = GPIOD_IS_OUT;
int ret;
dev_pdata = dev_get_platdata(dev);
uc_pdata = dev_get_uclass_platdata(dev);
if (!uc_pdata)
return -ENXIO;
/* Set type to fixed */
uc_pdata->type = REGULATOR_TYPE_FIXED;
if (dev_read_bool(dev, "enable-active-high"))
flags |= GPIOD_IS_OUT_ACTIVE;
/* Get fixed regulator optional enable GPIO desc */
gpio = &dev_pdata->gpio;
ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags);
if (ret) {
debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
ret);
if (ret != -ENOENT)
return ret;
}
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = dev_read_u32_default(dev,
"startup-delay-us", 0);
return 0;
}
static int stm32mp1_ddr_probe(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
struct regmap *map;
int ret;
debug("STM32MP1 DDR probe\n");
priv->dev = dev;
ret = regmap_init_mem(dev_ofnode(dev), &map);
if (ret)
return ret;
priv->ctl = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
priv->rcc = STM32_RCC_BASE;
priv->info.base = STM32_DDR_BASE;
#if !defined(CONFIG_STM32MP1_TRUSTED) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
priv->info.size = 0;
return stm32mp1_ddr_setup(dev);
#else
priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
return 0;
#endif
}
DEBUG_UART_FUNCS
#endif
#if CONFIG_IS_ENABLED(DM_SERIAL)
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
static int omap_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
fdt_addr_t addr;
struct clk clk;
int err;
/* try Processor Local Bus device first */
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = 2;
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
plat->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("omap serial failed to get clock\n");
return err;
}
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("omap serial clock not defined\n");
return -EINVAL;
}
plat->fcr = UART_FCR_DEFVAL;
return 0;
}
int i2c_chip_ofdata_to_platdata(struct udevice *dev, struct dm_i2c_chip *chip)
{
int addr;
chip->offset_len = dev_read_u32_default(dev, "u-boot,i2c-offset-len",
1);
chip->flags = 0;
addr = dev_read_u32_default(dev, "reg", -1);
if (addr == -1) {
debug("%s: I2C Node '%s' has no 'reg' property %s\n", __func__,
dev_read_name(dev), dev->name);
return -EINVAL;
}
chip->chip_addr = addr;
return 0;
}
static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
to_clk_fixed_rate(dev)->fixed_rate =
dev_read_u32_default(dev, "clock-frequency", 0);
#endif
return 0;
}
static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
host->name = dev->name;
host->ioaddr = dev_read_addr_ptr(dev);
host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
/* use non-removeable as sdcard and emmc as judgement */
if (dev_read_bool(dev, "non-removable"))
host->dev_index = 0;
else
host->dev_index = 1;
priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
if (priv->fifo_depth < 0)
return -EINVAL;
priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
/*
* 'clock-freq-min-max' is deprecated
* (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
*/
if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
if (val < 0)
return val;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = val;
} else {
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
return 0;
}
static int pm8916_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916";
return 0;
}
static int bcm6858_led_probe(struct udevice *dev)
{
struct led_uc_plat *uc_plat = dev_get_uclass_platdata(dev);
/* Top-level LED node */
if (!uc_plat->label) {
void __iomem *regs;
u32 set_bits = 0;
regs = dev_remap_addr(dev);
if (!regs)
return -EINVAL;
if (dev_read_bool(dev, "brcm,serial-led-msb-first"))
set_bits |= LED_CTRL_SERIAL_LED_MSB_FIRST;
if (dev_read_bool(dev, "brcm,serial-led-en-pol"))
set_bits |= LED_CTRL_SERIAL_LED_EN_POL;
if (dev_read_bool(dev, "brcm,serial-led-clk-pol"))
set_bits |= LED_CTRL_SERIAL_LED_CLK_POL;
if (dev_read_bool(dev, "brcm,serial-led-data-ppol"))
set_bits |= LED_CTRL_SERIAL_LED_DATA_PPOL;
if (dev_read_bool(dev, "brcm,led-test-mode"))
set_bits |= LED_CTRL_LED_TEST_MODE;
clrsetbits_32(regs + LED_CTRL_REG, ~0, set_bits);
} else {
struct bcm6858_led_priv *priv = dev_get_priv(dev);
void __iomem *regs;
unsigned int pin;
regs = dev_remap_addr(dev_get_parent(dev));
if (!regs)
return -EINVAL;
pin = dev_read_u32_default(dev, "reg", LEDS_MAX);
if (pin >= LEDS_MAX)
return -EINVAL;
priv->regs = regs;
priv->pin = pin;
/* this led is managed by software */
clrbits_32(regs + LED_HW_LED_EN_REG, 1 << pin);
/* configure the polarity */
if (dev_read_bool(dev, "active-low"))
clrbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin);
else
setbits_32(regs + LED_SW_LED_IP_PPOL_REG, 1 << pin);
}
return 0;
}
static int i2c_post_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency", 100000);
return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
#else
return 0;
#endif
}
int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg)
{
int val;
val = dev_read_u32_default(dev, "bus-width", 1);
switch (val) {
case 0x8:
cfg->host_caps |= MMC_MODE_8BIT;
/* fall through */
case 0x4:
cfg->host_caps |= MMC_MODE_4BIT;
/* fall through */
case 0x1:
cfg->host_caps |= MMC_MODE_1BIT;
break;
default:
dev_err(dev, "Invalid \"bus-width\" value %u!\n", val);
return -EINVAL;
}
/* f_max is obtained from the optional "max-frequency" property */
dev_read_u32(dev, "max-frequency", &cfg->f_max);
if (dev_read_bool(dev, "cap-sd-highspeed"))
cfg->host_caps |= MMC_CAP(SD_HS);
if (dev_read_bool(dev, "cap-mmc-highspeed"))
cfg->host_caps |= MMC_CAP(MMC_HS);
if (dev_read_bool(dev, "sd-uhs-sdr12"))
cfg->host_caps |= MMC_CAP(UHS_SDR12);
if (dev_read_bool(dev, "sd-uhs-sdr25"))
cfg->host_caps |= MMC_CAP(UHS_SDR25);
if (dev_read_bool(dev, "sd-uhs-sdr50"))
cfg->host_caps |= MMC_CAP(UHS_SDR50);
if (dev_read_bool(dev, "sd-uhs-sdr104"))
cfg->host_caps |= MMC_CAP(UHS_SDR104);
if (dev_read_bool(dev, "sd-uhs-ddr50"))
cfg->host_caps |= MMC_CAP(UHS_DDR50);
if (dev_read_bool(dev, "mmc-ddr-1_8v"))
cfg->host_caps |= MMC_CAP(MMC_DDR_52);
if (dev_read_bool(dev, "mmc-ddr-1_2v"))
cfg->host_caps |= MMC_CAP(MMC_DDR_52);
if (dev_read_bool(dev, "mmc-hs200-1_8v"))
cfg->host_caps |= MMC_CAP(MMC_HS_200);
if (dev_read_bool(dev, "mmc-hs200-1_2v"))
cfg->host_caps |= MMC_CAP(MMC_HS_200);
if (dev_read_bool(dev, "mmc-hs400-1_8v"))
cfg->host_caps |= MMC_CAP(MMC_HS_400);
if (dev_read_bool(dev, "mmc-hs400-1_2v"))
cfg->host_caps |= MMC_CAP(MMC_HS_400);
return 0;
}
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
debug("%s: start\n", __func__);
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret)
debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
}
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
&args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
}
priv->channel = args.args[0];
priv->period_ns = args.args[1];
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->default_level = fdt32_to_cpu(cell[index]);
priv->max_level = fdt32_to_cpu(cell[count - 1]);
} else {
priv->default_level = index;
priv->max_level = 255;
}
debug("%s: done\n", __func__);
return 0;
}
int syscon_reboot_probe(struct udevice *dev)
{
struct udevice *syscon;
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap", &syscon);
if (err) {
pr_err("unable to find syscon device\n");
return err;
}
priv->regmap = syscon_get_regmap(syscon);
if (!priv->regmap) {
pr_err("unable to find regmap\n");
return -ENODEV;
}
priv->offset = dev_read_u32_default(dev, "offset", 0);
priv->mask = dev_read_u32_default(dev, "mask", 0);
return 0;
}
static int bcm6345_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct bcm6345_gpio_priv *priv = dev_get_priv(dev);
priv->reg_dirout = dev_remap_addr_index(dev, 0);
if (!priv->reg_dirout)
return -EINVAL;
priv->reg_data = dev_remap_addr_index(dev, 1);
if (!priv->reg_data)
return -EINVAL;
uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios", 32);
uc_priv->bank_name = dev->name;
return 0;
}
static int ksz90x1_of_config_group(struct phy_device *phydev,
struct ksz90x1_ofcfg *ofcfg)
{
struct udevice *dev = phydev->dev;
struct phy_driver *drv = phydev->drv;
const int ps_to_regval = 60;
int val[4];
int i, changed = 0, offset, max;
u16 regval = 0;
if (!drv || !drv->writeext)
return -EOPNOTSUPP;
for (i = 0; i < ofcfg->grpsz; i++) {
val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
/* Default register value for KSZ9021 */
regval |= ofcfg->grp[i].dflt << offset;
} else {
changed = 1; /* Value was changed in OF */
/* Calculate the register value and fix corner cases */
max = (1 << ofcfg->grp[i].size) - 1;
if (val[i] > ps_to_regval * max) {
regval |= max << offset;
} else {
regval |= (val[i] / ps_to_regval) << offset;
}
}
}
if (!changed)
return 0;
return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
}
static int tegra_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct tegra_mmc_plat *plat = dev_get_platdata(dev);
struct tegra_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int bus_width, ret;
cfg->name = dev->name;
bus_width = dev_read_u32_default(dev, "bus-width", 1);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->host_caps = 0;
if (bus_width == 8)
cfg->host_caps |= MMC_MODE_8BIT;
if (bus_width >= 4)
cfg->host_caps |= MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
*/
cfg->f_min = 375000;
cfg->f_max = 48000000;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
priv->reg = (void *)dev_read_addr(dev);
ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
if (ret) {
debug("reset_get_by_name() failed: %d\n", ret);
return ret;
}
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret) {
debug("clk_get_by_index() failed: %d\n", ret);
return ret;
}
ret = reset_assert(&priv->reset_ctl);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
ret = clk_set_rate(&priv->clk, 20000000);
if (IS_ERR_VALUE(ret))
return ret;
ret = reset_deassert(&priv->reset_ctl);
if (ret)
return ret;
/* These GPIOs are optional */
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
GPIOD_IS_OUT);
if (dm_gpio_is_valid(&priv->pwr_gpio))
dm_gpio_set_value(&priv->pwr_gpio, 1);
upriv->mmc = &plat->mmc;
return tegra_mmc_init(dev);
}
static int stm32_sdmmc2_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
int ret;
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
if (dev_read_bool(dev, "st,negedge"))
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,dirpol"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
goto clk_free;
ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
if (ret)
goto clk_disable;
gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
GPIOD_IS_IN);
cfg->f_min = 400000;
cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->name = "STM32 SDMMC2";
cfg->host_caps = 0;
if (cfg->f_max > 25000000)
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_read_u32_default(dev, "bus-width", 1)) {
case 8:
cfg->host_caps |= MMC_MODE_8BIT;
case 4:
cfg->host_caps |= MMC_MODE_4BIT;
break;
case 1:
break;
default:
pr_err("invalid \"bus-width\" property, force to 1\n");
}
upriv->mmc = &plat->mmc;
return 0;
clk_disable:
clk_disable(&priv->clk);
clk_free:
clk_free(&priv->clk);
return ret;
}
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
{
struct stm32_sdram_params *params = dev_get_platdata(dev);
struct bank_params *bank_params;
struct ofnode_phandle_args args;
u32 *syscfg_base;
u32 mem_remap;
u32 swp_fmc;
ofnode bank_node;
char *bank_name;
u8 bank = 0;
int ret;
ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (ret) {
dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
} else {
syscfg_base = (u32 *)ofnode_get_addr(args.node);
mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
if (mem_remap != NOT_FOUND) {
/* set memory mapping selection */
clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
} else {
dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
}
swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
if (swp_fmc != NOT_FOUND) {
/* set fmc swapping selection */
clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
} else {
dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
}
dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
}
dev_for_each_subnode(bank_node, dev) {
/* extract the bank index from DT */
bank_name = (char *)ofnode_get_name(bank_node);
strsep(&bank_name, "@");
if (!bank_name) {
pr_err("missing sdram bank index");
return -EINVAL;
}
bank_params = ¶ms->bank_params[bank];
strict_strtoul(bank_name, 10,
(long unsigned int *)&bank_params->target_bank);
if (bank_params->target_bank >= MAX_SDRAM_BANK) {
pr_err("Found bank %d , but only bank 0 and 1 are supported",
bank_params->target_bank);
return -EINVAL;
}
debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
params->bank_params[bank].sdram_control =
(struct stm32_sdram_control *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-control",
sizeof(struct stm32_sdram_control));
if (!params->bank_params[bank].sdram_control) {
pr_err("st,sdram-control not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
params->bank_params[bank].sdram_timing =
(struct stm32_sdram_timing *)
ofnode_read_u8_array_ptr(bank_node,
"st,sdram-timing",
sizeof(struct stm32_sdram_timing));
if (!params->bank_params[bank].sdram_timing) {
pr_err("st,sdram-timing not found for %s",
ofnode_get_name(bank_node));
return -EINVAL;
}
bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
"st,sdram-refcount", 8196);
bank++;
}
int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
{
struct ns16550_platdata *plat = dev->platdata;
const u32 port_type = dev_get_driver_data(dev);
fdt_addr_t addr;
struct clk clk;
int err;
/* try Processor Local Bus device first */
addr = dev_read_addr(dev);
#if defined(CONFIG_PCI) && defined(CONFIG_DM_PCI)
if (addr == FDT_ADDR_T_NONE) {
/* then try pci device */
struct fdt_pci_addr pci_addr;
u32 bar;
int ret;
/* we prefer to use a memory-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
dev_of_offset(dev),
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
return ret;
}
ret = fdtdec_get_pci_bar32(dev, &pci_addr, &bar);
if (ret)
return ret;
addr = bar;
}
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
plat->base = addr;
#else
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
if (!err) {
err = clk_get_rate(&clk);
if (!IS_ERR_VALUE(err))
plat->clock = err;
} else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
debug("ns16550 failed to get clock\n");
return err;
}
if (!plat->clock)
plat->clock = dev_read_u32_default(dev, "clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
debug("ns16550 clock not defined\n");
return -EINVAL;
}
plat->fcr = UART_FCR_DEFVAL;
if (port_type == PORT_JZ4780)
plat->fcr |= UART_FCR_UME;
return 0;
}
static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
{
struct ddr_info *priv = dev_get_priv(dev);
int ret, idx;
struct clk axidcg;
struct stm32mp1_ddr_config config;
#define PARAM(x, y) \
{ x,\
offsetof(struct stm32mp1_ddr_config, y),\
sizeof(config.y) / sizeof(u32)}
#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
const struct {
const char *name; /* name in DT */
const u32 offset; /* offset in config struct */
const u32 size; /* size of parameters */
} param[] = {
CTL_PARAM(reg),
CTL_PARAM(timing),
CTL_PARAM(map),
CTL_PARAM(perf),
PHY_PARAM(reg),
PHY_PARAM(timing),
PHY_PARAM(cal)
};
config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
config.info.name = dev_read_string(dev, "st,mem-name");
if (!config.info.name) {
debug("%s: no st,mem-name\n", __func__);
return -EINVAL;
}
printf("RAM: %s\n", config.info.name);
for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
ret = dev_read_u32_array(dev, param[idx].name,
(void *)((u32)&config +
param[idx].offset),
param[idx].size);
debug("%s: %s[0x%x] = %d\n", __func__,
param[idx].name, param[idx].size, ret);
if (ret) {
pr_err("%s: Cannot read %s\n",
__func__, param[idx].name);
return -EINVAL;
}
}
ret = clk_get_by_name(dev, "axidcg", &axidcg);
if (ret) {
debug("%s: Cannot found axidcg\n", __func__);
return -EINVAL;
}
clk_disable(&axidcg); /* disable clock gating during init */
stm32mp1_ddr_init(priv, &config);
clk_enable(&axidcg); /* enable clock gating */
/* check size */
debug("%s : get_ram_size(%x, %x)\n", __func__,
(u32)priv->info.base, (u32)STM32_DDR_SIZE);
priv->info.size = get_ram_size((long *)priv->info.base,
STM32_DDR_SIZE);
debug("%s : %x\n", __func__, (u32)priv->info.size);
/* check memory access for all memory */
if (config.info.size != priv->info.size) {
printf("DDR invalid size : 0x%x, expected 0x%x\n",
priv->info.size, config.info.size);
return -EINVAL;
}
return 0;
}
