static void
awin_gige_pmu_init(device_t dev)
{
if (awin_chip_id() == AWIN_CHIP_ID_A80) {
#if NAXP806PM > 0
device_t axp806 = device_find_by_driver_unit("axp806pm", 0);
if (axp806) {
struct axp806_ctrl *c = axp806_lookup(axp806, "CLDO1");
if (c) {
axp806_set_voltage(c, 3000, 3000);
axp806_enable(c);
delay(3000);
}
}
#endif
#if NAXP809PM > 0
device_t axp809 = device_find_by_driver_unit("axp809pm", 0);
if (axp809) {
struct axp809_ctrl *c = axp809_lookup(axp809, "GPIO1");
if (c) {
axp809_enable(c);
delay(3000);
}
}
#endif
delay(100000);
}
}
void
tegra_mpio_dump(void)
{
const struct tegra_mpio_padgrp *pg;
const struct tegra_mpio_pinmux *pm;
struct tegra_mpio_padctlgrp ctl;
const char *func;
int config;
device_t dev;
u_int n;
dev = device_find_by_driver_unit("tegrampio", 0);
if (dev == NULL)
return;
printf("Dumping pad groups:\n");
for (n = 0; n < __arraycount(tegra_mpio_padgrp); n++) {
pg = &tegra_mpio_padgrp[n];
tegra_mpio_padctlgrp_read(pg->pg_reg, &ctl);
printf(" #%u [+%#x]: preemp=%d, hsm=%d, schmt=%d,"
" drv_type=%d, drvdn=%d, drvup=%d, slwr=%d, slwf=%d\n",
n, pg->pg_reg, ctl.preemp, ctl.hsm, ctl.schmt,
ctl.drv_type, ctl.drvdn, ctl.drvup, ctl.slwr, ctl.slwf);
}
printf("Dumping pin muxes:\n");
for (n = 0; n < __arraycount(tegra_mpio_pinmux); n++) {
pm = &tegra_mpio_pinmux[n];
tegra_mpio_pinmux_get_config(pm->pm_reg, &config, &func);
printf(" #%u [+%#x]: config=%#x func=%s\n",
n, pm->pm_reg, config, func);
}
}
static struct tegra_mpio_softc *
tegra_mpio_lookup_softc(void)
{
device_t dev = device_find_by_driver_unit("tegrampio", 0);
KASSERT(dev != NULL);
return device_private(dev);
}
static void
get_device(char *name)
{
int unit, part;
char devname[16], *cp;
device_t dv;
if (strncmp(name, "/dev/", 5) == 0)
name += 5;
if (devsw_name2blk(name, devname, sizeof(devname)) == -1)
return;
name += strlen(devname);
unit = part = 0;
cp = name;
while (*cp >= '0' && *cp <= '9')
unit = (unit * 10) + (*cp++ - '0');
if (cp == name)
return;
if (*cp >= 'a' && *cp < ('a' + MAXPARTITIONS))
part = *cp - 'a';
else if (*cp != '\0' && *cp != ' ')
return;
if ((dv = device_find_by_driver_unit(devname, unit)) != NULL) {
booted_device = dv;
booted_partition = part;
}
}
void
awin_hdmi_get_info(struct awin_hdmi_info *info)
{
struct awin_hdmi_softc *sc;
device_t dev;
memset(info, 0, sizeof(*info));
dev = device_find_by_driver_unit("awinhdmi", 0);
if (dev == NULL) {
info->display_connected = false;
return;
}
sc = device_private(dev);
info->display_connected = sc->sc_connected;
if (info->display_connected) {
strlcpy(info->display_vendor, sc->sc_display_vendor,
sizeof(info->display_vendor));
strlcpy(info->display_product, sc->sc_display_product,
sizeof(info->display_product));
info->display_hdmimode =
sc->sc_current_display_mode == DISPLAY_MODE_HDMI;
}
}
struct tegra_gpio_pin *
tegra_gpio_acquire(const char *pinname, u_int flags)
{
struct tegra_gpio_bank bank;
struct tegra_gpio_pin *gpin;
int pin;
device_t dev;
dev = device_find_by_driver_unit("tegragpio", 0);
if (dev == NULL)
return NULL;
bank.bank_sc = device_private(dev);
bank.bank_pb = tegra_gpio_pin_lookup(pinname, &pin);
if (bank.bank_pb == NULL)
return NULL;
const uint32_t cnf = GPIO_READ(&bank, GPIO_CNF_REG);
if ((cnf & __BIT(pin)) == 0)
GPIO_WRITE(&bank, GPIO_CNF_REG, cnf | __BIT(pin));
gpin = kmem_alloc(sizeof(*gpin), KM_SLEEP);
gpin->pin_bank = bank;
gpin->pin_no = pin;
gpin->pin_flags = flags;
tegra_gpio_pin_ctl(&gpin->pin_bank, gpin->pin_no, gpin->pin_flags);
return gpin;
}
struct bcm_pwm_channel *
bcm_pwm_alloc(int num)
{
struct bcm2835pwm_softc *sc;
device_t dev;
struct bcm_pwm_channel *pwm;
dev = device_find_by_driver_unit("bcmpwm", 0);
if (dev == NULL)
return NULL;
sc = device_private(dev);
if (num < 0 || num >= __arraycount(sc->sc_channels))
return NULL;
pwm = &sc->sc_channels[num];
mutex_enter(&sc->sc_lock);
if (pwm->inuse)
pwm = NULL;
else
pwm->inuse = true;
mutex_exit(&sc->sc_lock);
if (pwm) {
pwm->datsave = PWM_READ(pwm->sc, pwm->dat);
pwm->ctlsave = PWM_READ(pwm->sc, PWM_CTL);
pwm->rngsave = PWM_READ(pwm->sc, pwm->rng);
}
return pwm;
}
void
awin_hdmi_dump_regs(void)
{
static const struct {
const char *name;
uint16_t reg;
} regs[] = {
{ "CTRL", AWIN_HDMI_CTRL_REG },
{ "INT_STATUS", AWIN_HDMI_INT_STATUS_REG },
{ "VID_CTRL", AWIN_HDMI_VID_CTRL_REG },
{ "VID_TIMING_0", AWIN_HDMI_VID_TIMING_0_REG },
{ "VID_TIMING_1", AWIN_HDMI_VID_TIMING_1_REG },
{ "VID_TIMING_2", AWIN_HDMI_VID_TIMING_2_REG },
{ "VID_TIMING_3", AWIN_HDMI_VID_TIMING_3_REG },
{ "VID_TIMING_4", AWIN_HDMI_VID_TIMING_4_REG },
{ "PAD_CTRL0", AWIN_HDMI_PAD_CTRL0_REG },
{ "PAD_CTRL1", AWIN_HDMI_PAD_CTRL1_REG },
{ "PLL_CTRL", AWIN_HDMI_PLL_CTRL_REG },
{ "PLL_DBG0", AWIN_HDMI_PLL_DBG0_REG },
{ "PLL_DBG1", AWIN_HDMI_PLL_DBG1_REG },
};
struct awin_hdmi_softc *sc;
device_t dev;
dev = device_find_by_driver_unit("awinhdmi", 0);
if (dev == NULL)
return;
sc = device_private(dev);
for (int i = 0; i < __arraycount(regs); i++) {
printf("%s: 0x%08x\n", regs[i].name,
HDMI_READ(sc, regs[i].reg));
}
}
static void
awin_fb_attach(device_t parent, device_t self, void *aux)
{
struct awin_fb_softc *sc = device_private(self);
struct awinfb_attach_args * const afb = aux;
prop_dictionary_t cfg = device_properties(self);
struct genfb_ops ops;
if (awin_fb_consoledev == NULL)
awin_fb_consoledev = self;
sc->sc_gen.sc_dev = self;
sc->sc_debedev = parent;
sc->sc_dmat = afb->afb_dmat;
sc->sc_dmasegs = afb->afb_dmasegs;
sc->sc_ndmasegs = afb->afb_ndmasegs;
sc->sc_mpdev = device_find_by_driver_unit("awinmp", 0);
prop_dictionary_set_uint32(cfg, "width", afb->afb_width);
prop_dictionary_set_uint32(cfg, "height", afb->afb_height);
prop_dictionary_set_uint8(cfg, "depth", 32);
prop_dictionary_set_uint16(cfg, "linebytes", afb->afb_width * 4);
prop_dictionary_set_uint32(cfg, "address", 0);
prop_dictionary_set_uint32(cfg, "virtual_address",
(uintptr_t)afb->afb_fb);
genfb_init(&sc->sc_gen);
if (sc->sc_gen.sc_width == 0 || sc->sc_gen.sc_fbsize == 0) {
aprint_normal(": disabled\n");
return;
}
pmf_device_register1(self, NULL, NULL, awin_fb_shutdown);
memset(&ops, 0, sizeof(ops));
ops.genfb_ioctl = awin_fb_ioctl;
ops.genfb_mmap = awin_fb_mmap;
aprint_naive("\n");
bool is_console = false;
prop_dictionary_get_bool(cfg, "is_console", &is_console);
if (is_console)
aprint_normal(": switching to framebuffer console\n");
else
aprint_normal("\n");
genfb_attach(&sc->sc_gen, &ops);
}
static void
awin_tve_i2c_init(struct awin_tve_softc *sc)
{
device_t iic2;
sc->sc_i2c = NULL;
iic2 = device_find_by_driver_unit("awiniic", 2);
if (iic2 == NULL)
return;
sc->sc_i2c = awin_twi_get_controller(iic2);
}
struct bcm_dmac_channel *
bcm_dmac_alloc(enum bcm_dmac_type type, int ipl, void (*cb)(void *),
void *cbarg)
{
struct bcm_dmac_softc *sc;
struct bcm_dmac_channel *ch = NULL;
device_t dev;
int index;
dev = device_find_by_driver_unit("bcmdmac", 0);
if (dev == NULL)
return NULL;
sc = device_private(dev);
mutex_enter(&sc->sc_lock);
for (index = 0; index < sc->sc_nchannels; index++) {
if ((sc->sc_channelmask & __BIT(index)) == 0)
continue;
if (DMAC_CHANNEL_TYPE(&sc->sc_channels[index]) != type)
continue;
if (DMAC_CHANNEL_USED(&sc->sc_channels[index]))
continue;
ch = &sc->sc_channels[index];
ch->ch_callback = cb;
ch->ch_callbackarg = cbarg;
break;
}
mutex_exit(&sc->sc_lock);
if (ch == NULL)
return NULL;
KASSERT(ch->ch_ih == NULL);
ch->ch_ih = bcm2835_intr_establish(BCM2835_INT_DMA0 + ch->ch_index,
ipl, bcm_dmac_intr, ch);
if (ch->ch_ih == NULL) {
aprint_error_dev(sc->sc_dev,
"failed to establish interrupt for DMA%d\n", ch->ch_index);
ch->ch_callback = NULL;
ch->ch_callbackarg = NULL;
ch = NULL;
}
return ch;
}
int
bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp)
{
struct bcm2835cm_softc *sc;
device_t dev;
int ctlreg, divreg;
dev = device_find_by_driver_unit("bcmcm", 0);
if (dev == NULL)
return ENXIO;
sc = device_private(dev);
switch (clk) {
case BCM_CM_GP0:
ctlreg = CM_GP0CTL;
divreg = CM_GP0DIV;
break;
case BCM_CM_GP1:
ctlreg = CM_GP1CTL;
divreg = CM_GP1DIV;
break;
case BCM_CM_GP2:
ctlreg = CM_GP2CTL;
divreg = CM_GP2DIV;
break;
case BCM_CM_PCM:
ctlreg = CM_PCMCTL;
divreg = CM_PCMDIV;
break;
case BCM_CM_PWM:
ctlreg = CM_PWMCTL;
divreg = CM_PWMDIV;
break;
default:
return EINVAL;
}
if (ctlp != NULL)
*ctlp = CM_READ(sc, ctlreg);
if (divp != NULL)
*divp = CM_READ(sc, divreg);
return 0;
}
static void
findbootdev(void)
{
device_t dv;
int major, unit, controller;
const char *name;
booted_device = NULL;
booted_partition = 0; /* Assume root is on partition a */
major = B_TYPE(bootdev);
name = devsw_blk2name(major);
if (name == NULL)
return;
unit = B_UNIT(bootdev);
switch (major) {
case 4: /* SCSI drive */
#if NSCSIBUS > 0
bootdev &= ~(B_UNITMASK << B_UNITSHIFT); /* XXX */
unit = target_to_unit(-1, unit, 0);
bootdev |= (unit << B_UNITSHIFT); /* XXX */
#else /* NSCSIBUS > 0 */
panic("Boot device is on a SCSI drive but SCSI support "
"is not present");
#endif /* NSCSIBUS > 0 */
break;
case 22: /* IDE drive */
/*
* controller(=channel=buses) uses only IDE drive.
* Here, controller always is 0.
*/
controller = B_CONTROLLER(bootdev);
unit = unit + (controller<<1);
break;
}
if ((dv = device_find_by_driver_unit(name, unit)) != NULL)
booted_device = dv;
}
void
bcm_dmac_dump_regs(void)
{
struct bcm_dmac_softc *sc;
device_t dev;
int index;
dev = device_find_by_driver_unit("bcmdmac", 0);
if (dev == NULL)
return;
sc = device_private(dev);
for (index = 0; index < sc->sc_nchannels; index++) {
if ((sc->sc_channelmask & __BIT(index)) == 0)
continue;
printf("%d_CS: %08X\n", index,
DMAC_READ(sc, DMAC_CS(index)));
printf("%d_CONBLK_AD: %08X\n", index,
DMAC_READ(sc, DMAC_CONBLK_AD(index)));
printf("%d_DEBUG: %08X\n", index,
DMAC_READ(sc, DMAC_DEBUG(index)));
}
}
/*
* SCSI device: The controller number corresponds to the
* scsibus number, and the unit number is (targ*8 + LUN).
*/
static device_t
scsi_find(char *name, int ctlr, int unit)
{
device_t scsibus;
struct scsibus_softc *sbsc;
struct scsipi_periph *periph;
int target, lun;
if ((scsibus = device_find_by_driver_unit("scsibus", ctlr)) == NULL)
return NULL;
/* Compute SCSI target/LUN from PROM unit. */
target = prom_sd_target((unit >> 3) & 7);
lun = unit & 7;
/* Find the device at this target/LUN */
sbsc = device_private(scsibus);
periph = scsipi_lookup_periph(sbsc->sc_channel, target, lun);
if (periph == NULL)
return NULL;
return periph->periph_dev;
}
static u_int
rk3188_cpu_set_rate(u_int rate)
{
const struct rk3188_apll_rate *r = NULL;
uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
uint32_t reset_mask, reset, status0_reg, status0_apll_lock;
u_int cpu_aclk_div_con;
u_int old_rate = rk3188_cpu_get_rate();
u_int new_rate;
#if NACT8846PM > 0
device_t pmic;
struct act8846_ctrl *dcdc3;
pmic = device_find_by_driver_unit("act8846pm", 0);
if (pmic == NULL) {
printf("%s: no PMIC driver found\n", __func__);
return ENXIO;
}
dcdc3 = act8846_lookup(pmic, "DCDC3");
KASSERT(dcdc3 != NULL);
#endif
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("%s: rate=%u\n", __func__, rate);
#endif
/* Pick the closest rate (nearest 100MHz increment) */
for (int i = 0; i < __arraycount(rk3188_apll_rates); i++) {
u_int arate = ((rk3188_apll_rates[i].rate / 1000000) + 50)
/ 100 * 100;
if (arate <= rate) {
r = &rk3188_apll_rates[i];
break;
}
}
if (r == NULL) {
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("CPU: No matching rate found for %u MHz\n", rate);
#endif
return EINVAL;
}
switch (rockchip_chip_id()) {
case ROCKCHIP_CHIP_ID_RK3066:
case ROCKCHIP_CHIP_ID_RK3188PLUS:
reset_mask = CRU_PLL_CON3_RESET_MASK;
reset = CRU_PLL_CON3_RESET;
apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
apll_con0 |= __SHIFTIN(r->no - 1, CRU_PLL_CON0_CLKOD);
apll_con1 = CRU_PLL_CON1_CLKF_MASK;
apll_con1 |= __SHIFTIN(r->nf - 1, CRU_PLL_CON1_CLKF);
apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
apll_con2 |= __SHIFTIN(r->nf >> 1, CRU_PLL_CON2_BWADJ);
break;
case ROCKCHIP_CHIP_ID_RK3188:
reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
reset = CRU_PLL_CON3_POWER_DOWN;
apll_con0 =
CRU_PLL_CON0_CLKR_MASK | RK3188_CRU_PLL_CON0_CLKOD_MASK;
apll_con0 |= __SHIFTIN(r->nr - 1, CRU_PLL_CON0_CLKR);
apll_con0 |= __SHIFTIN(r->no - 1, RK3188_CRU_PLL_CON0_CLKOD);
apll_con1 = RK3188_CRU_PLL_CON1_CLKF_MASK;
apll_con1 |= __SHIFTIN(r->nf - 1, RK3188_CRU_PLL_CON1_CLKF);
apll_con2 = 0;
break;
default:
return EINVAL;
}
switch (r->core_axi_div) {
case 1: cpu_aclk_div_con = 0; break;
case 2: cpu_aclk_div_con = 1; break;
case 3: cpu_aclk_div_con = 2; break;
case 4: cpu_aclk_div_con = 3; break;
case 8: cpu_aclk_div_con = 4; break;
default: panic("bad core_axi_div");
}
switch (rockchip_chip_id()) {
case ROCKCHIP_CHIP_ID_RK3066:
clksel0_con = CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
clksel0_con |= __SHIFTIN(r->core_div - 1,
CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
status0_reg = GRF_STATUS0_REG;
status0_apll_lock = GRF_STATUS0_APLL_LOCK;
break;
case ROCKCHIP_CHIP_ID_RK3188:
case ROCKCHIP_CHIP_ID_RK3188PLUS:
clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK;
clksel0_con |= __SHIFTIN(r->core_div - 1,
RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
clksel0_con |= __SHIFTIN(ffs(r->core_periph_div) - 2,
CRU_CLKSEL_CON0_CORE_PERI_DIV_CON);
clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK |
RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK;
clksel1_con |= __SHIFTIN(ffs(r->ahb2apb_div) - 1,
CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(r->hclk_div) - 1,
CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(r->pclk_div) - 1,
CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON);
clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
status0_reg = RK3188_GRF_STATUS0_REG;
status0_apll_lock = RK3188_GRF_STATUS0_APLL_LOCK;
break;
default:
return EINVAL;
}
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("%s: Set frequency to %u MHz...\n", __func__, r->rate);
printf("before: APLL_CON0: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON0_REG));
printf("before: APLL_CON1: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON1_REG));
printf("before: CLKSEL0_CON: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0)));
printf("before: CLKSEL1_CON: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1)));
#endif
new_rate = r->rate / 1000000;
if (new_rate > old_rate) {
#if NACT8846PM > 0
act8846_set_voltage(dcdc3, r->voltage, r->voltage);
#endif
}
bus_space_write_4(bst, cru_bsh, CRU_MODE_CON_REG,
CRU_MODE_CON_APLL_WORK_MODE_MASK |
__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
CRU_MODE_CON_APLL_WORK_MODE));
/* Power down */
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON3_REG, reset_mask | reset);
/* Update APLL regs */
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON0_REG, apll_con0);
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON1_REG, apll_con1);
if (apll_con2)
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON2_REG, apll_con2);
for (volatile int i = 5000; i >= 0; i--)
;
/* Power up */
bus_space_write_4(bst, cru_bsh, CRU_APLL_CON3_REG, reset_mask);
/* Wait for PLL lock */
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("%s: Waiting for PLL lock...\n", __func__);
#endif
for (volatile int i = 50000; i >= 0; i--)
;
int retry = ROCKCHIP_REF_FREQ;
while (--retry > 0) {
uint32_t status = bus_space_read_4(bst, grf_bsh, status0_reg);
if (status & status0_apll_lock)
break;
}
if (retry == 0)
printf("%s: PLL lock timeout\n", __func__);
/* Update CLKSEL regs */
bus_space_write_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0), clksel0_con);
bus_space_write_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1), clksel1_con);
/* Slow -> Normal mode */
bus_space_write_4(bst, cru_bsh, CRU_MODE_CON_REG,
CRU_MODE_CON_APLL_WORK_MODE_MASK |
__SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_NORMAL,
CRU_MODE_CON_APLL_WORK_MODE));
#ifdef ROCKCHIP_CLOCK_DEBUG
printf("after: APLL_CON0: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON0_REG));
printf("after: APLL_CON1: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_APLL_CON1_REG));
printf("after: CLKSEL0_CON: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(0)));
printf("after: CLKSEL1_CON: %#x\n",
bus_space_read_4(bst, cru_bsh, CRU_CLKSEL_CON_REG(1)));
#endif
a9tmr_update_freq(rockchip_a9periph_get_rate());
#if NACT8846PM > 0
if (new_rate < old_rate) {
act8846_set_voltage(dcdc3, r->voltage, r->voltage);
}
#endif
return 0;
}
void
awin_tcon1_enable(int unit, bool enable)
{
struct awin_tcon_softc *sc;
device_t dev;
uint32_t val;
dev = device_find_by_driver_unit("awintcon", unit);
if (dev == NULL) {
printf("TCON%d: no driver found\n", unit);
return;
}
sc = device_private(dev);
KASSERT((sc->sc_output_type == OUTPUT_HDMI) ||
(sc->sc_output_type == OUTPUT_VGA));
awin_debe_enable(device_unit(sc->sc_dev), enable);
delay(20000);
if (enable) {
val = TCON_READ(sc, AWIN_TCON_GCTL_REG);
val |= AWIN_TCON_GCTL_EN;
TCON_WRITE(sc, AWIN_TCON_GCTL_REG, val);
val = TCON_READ(sc, AWIN_TCON1_CTL_REG);
val |= AWIN_TCONx_CTL_EN;
TCON_WRITE(sc, AWIN_TCON1_CTL_REG, val);
if (sc->sc_output_type == OUTPUT_VGA) {
TCON_WRITE(sc, AWIN_TCON1_IO_TRI_REG, 0x0cffffff);
} else
TCON_WRITE(sc, AWIN_TCON1_IO_TRI_REG, 0);
} else {
TCON_WRITE(sc, AWIN_TCON1_IO_TRI_REG, 0xffffffff);
val = TCON_READ(sc, AWIN_TCON1_CTL_REG);
val &= ~AWIN_TCONx_CTL_EN;
TCON_WRITE(sc, AWIN_TCON1_CTL_REG, val);
val = TCON_READ(sc, AWIN_TCON_GCTL_REG);
val &= ~AWIN_TCON_GCTL_EN;
TCON_WRITE(sc, AWIN_TCON_GCTL_REG, val);
}
KASSERT(tcon_mux_inited);
val = bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0);
#ifdef AWIN_TCON_DEBUG
printf("awin_tcon1_enable(%d) %d val 0x%x", unit, enable, val);
#endif
val &= ~ AWIN_TCON_MUX_CTL_HDMI_OUTPUT_SRC;
if (unit == 0) {
val |= __SHIFTIN(AWIN_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1,
AWIN_TCON_MUX_CTL_HDMI_OUTPUT_SRC);
} else if (unit == 1) {
val |= __SHIFTIN(AWIN_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1,
AWIN_TCON_MUX_CTL_HDMI_OUTPUT_SRC);
}
#ifdef AWIN_TCON_DEBUG
printf(" -> 0x%x", val);
#endif
bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, val);
#ifdef AWIN_TCON_DEBUG
printf(": 0x%" PRIxBSH " 0x%" PRIxBSH " 0x%x 0x%x\n", sc->sc_bsh,
tcon_mux_bsh, bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0),
TCON_READ(sc, AWIN_TCON_MUX_CTL_REG));
#endif
}
int
bcm_cm_set(enum bcm_cm_clock clk, uint32_t ctl, uint32_t div)
{
struct bcm2835cm_softc *sc;
device_t dev;
int ctlreg, divreg;
uint32_t r;
dev = device_find_by_driver_unit("bcmcm", 0);
if (dev == NULL)
return ENXIO;
sc = device_private(dev);
switch (clk) {
case BCM_CM_GP0:
ctlreg = CM_GP0CTL;
divreg = CM_GP0DIV;
break;
case BCM_CM_GP1:
ctlreg = CM_GP1CTL;
divreg = CM_GP1DIV;
break;
case BCM_CM_GP2:
ctlreg = CM_GP2CTL;
divreg = CM_GP2DIV;
break;
case BCM_CM_PCM:
ctlreg = CM_PCMCTL;
divreg = CM_PCMDIV;
break;
case BCM_CM_PWM:
ctlreg = CM_PWMCTL;
divreg = CM_PWMDIV;
break;
default:
return EINVAL;
}
ctl &= ~CM_CTL_PASSWD;
ctl |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);
div &= ~CM_DIV_PASSWD;
div |= __SHIFTIN(CM_PASSWD, CM_DIV_PASSWD);
/* if clock is running, turn it off and wait for
* the cycle to end
*/
r = CM_READ(sc, ctlreg);
if (r & CM_CTL_ENAB) {
r &= ~CM_CTL_PASSWD;
r |= __SHIFTIN(CM_PASSWD, CM_CTL_PASSWD);
r &= ~CM_CTL_ENAB;
CM_WRITE(sc, ctlreg, r);
}
bcmcm_wait(sc, ctlreg, 0);
/* configure new divider, mode, don't enable */
CM_WRITE(sc, divreg, div);
CM_WRITE(sc, ctlreg, ctl & ~CM_CTL_ENAB);
/* enable it */
if (ctl & CM_CTL_ENAB) {
CM_WRITE(sc, ctlreg, ctl);
return bcmcm_wait(sc, ctlreg, 1);
}
return 0;
}
void
awin_tcon1_set_videomode(int unit, const struct videomode *mode)
{
struct awin_tcon_softc *sc;
device_t dev;
uint32_t val;
dev = device_find_by_driver_unit("awintcon", unit);
if (dev == NULL) {
printf("TCON%d: no driver found\n", unit);
return;
}
sc = device_private(dev);
KASSERT((sc->sc_output_type == OUTPUT_HDMI) ||
(sc->sc_output_type == OUTPUT_VGA));
awin_debe_set_videomode(device_unit(sc->sc_dev), mode);
if (mode) {
const u_int interlace_p = !!(mode->flags & VID_INTERLACE);
const u_int phsync_p = !!(mode->flags & VID_PHSYNC);
const u_int pvsync_p = !!(mode->flags & VID_PVSYNC);
const u_int hspw = mode->hsync_end - mode->hsync_start;
const u_int hbp = mode->htotal - mode->hsync_start;
const u_int vspw = mode->vsync_end - mode->vsync_start;
const u_int vbp = mode->vtotal - mode->vsync_start;
const u_int vblank_len =
((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2;
const u_int start_delay =
vblank_len >= 32 ? 30 : vblank_len - 2;
val = TCON_READ(sc, AWIN_TCON_GCTL_REG);
val |= AWIN_TCON_GCTL_IO_MAP_SEL;
TCON_WRITE(sc, AWIN_TCON_GCTL_REG, val);
/* enable */
val = AWIN_TCONx_CTL_EN;
if (interlace_p)
val |= AWIN_TCONx_CTL_INTERLACE_EN;
val |= __SHIFTIN(start_delay, AWIN_TCONx_CTL_START_DELAY);
#ifdef AWIN_TCON1_BLUEDATA
val |= __SHIFTIN(AWIN_TCONx_CTL_SRC_SEL_BLUEDATA,
AWIN_TCONx_CTL_SRC_SEL);
#else
/*
* the DE selector selects the primary DEBE for this tcon:
* 0 selects debe0 for tcon0 and debe1 for tcon1
*/
val |= __SHIFTIN(AWIN_TCONx_CTL_SRC_SEL_DE0,
AWIN_TCONx_CTL_SRC_SEL);
#endif
TCON_WRITE(sc, AWIN_TCON1_CTL_REG, val);
/* Source width/height */
TCON_WRITE(sc, AWIN_TCON1_BASIC0_REG,
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
/* Scaler width/height */
TCON_WRITE(sc, AWIN_TCON1_BASIC1_REG,
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
/* Output width/height */
TCON_WRITE(sc, AWIN_TCON1_BASIC2_REG,
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
/* Horizontal total + back porch */
TCON_WRITE(sc, AWIN_TCON1_BASIC3_REG,
((mode->htotal - 1) << 16) | (hbp - 1));
/* Vertical total + back porch */
u_int vtotal = mode->vtotal * 2;
if (interlace_p) {
u_int framerate =
DIVIDE(DIVIDE(mode->dot_clock * 1000, mode->htotal),
mode->vtotal);
u_int clk = mode->htotal * (mode->vtotal * 2 + 1) *
framerate;
if ((clk / 2) == mode->dot_clock * 1000)
vtotal += 1;
}
TCON_WRITE(sc, AWIN_TCON1_BASIC4_REG,
(vtotal << 16) | (vbp - 1));
/* Sync */
TCON_WRITE(sc, AWIN_TCON1_BASIC5_REG,
((hspw - 1) << 16) | (vspw - 1));
/* Polarity */
val = AWIN_TCON_IO_POL_IO2_INV;
if (phsync_p)
val |= AWIN_TCON_IO_POL_PHSYNC;
if (pvsync_p)
val |= AWIN_TCON_IO_POL_PVSYNC;
TCON_WRITE(sc, AWIN_TCON1_IO_POL_REG, val);
TCON_WRITE(sc, AWIN_TCON_GINT1_REG,
__SHIFTIN(start_delay + 2, AWIN_TCON_GINT1_TCON1_LINENO));
/* Setup LCDx CH1 PLL */
awin_tcon_set_pll(sc, mode->dot_clock, 1);
} else {
/*
* Xylogics SMD disk: (xy, xd)
* Assume wired-in unit numbers for now...
*/
static device_t
xx_find(char *name, int ctlr, int unit)
{
return device_find_by_driver_unit(name, ctlr * 2 + unit);
}
