static int scpi_clk_add(struct device *dev, struct device_node *np,
const struct of_device_id *match)
{
struct clk **clks;
int idx, count;
struct scpi_clk_data *clk_data;
count = of_property_count_strings(np, "clock-output-names");
if (count < 0) {
dev_err(dev, "%s: invalid clock output count\n", np->name);
return -EINVAL;
}
clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->clk_num = count;
clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk),
GFP_KERNEL);
if (!clk_data->clk)
return -ENOMEM;
clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL);
if (!clks)
return -ENOMEM;
for (idx = 0; idx < count; idx++) {
struct scpi_clk *sclk;
const char *name;
u32 val;
sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL);
if (!sclk)
return -ENOMEM;
if (of_property_read_string_index(np, "clock-output-names",
idx, &name)) {
dev_err(dev, "invalid clock name @ %s\n", np->name);
return -EINVAL;
}
if (of_property_read_u32_index(np, "clock-indices",
idx, &val)) {
dev_err(dev, "invalid clock index @ %s\n", np->name);
return -EINVAL;
}
sclk->id = val;
clks[idx] = scpi_clk_ops_init(dev, match, sclk, name);
if (IS_ERR_OR_NULL(clks[idx]))
dev_err(dev, "failed to register clock '%s'\n", name);
else
dev_dbg(dev, "Registered clock '%s'\n", name);
clk_data->clk[idx] = sclk;
}
return of_clk_add_provider(np, scpi_of_clk_src_get, clk_data);
}
static struct xgbe_channel *xgbe_alloc_rings(struct xgbe_prv_data *pdata)
{
struct xgbe_channel *channel_mem, *channel;
struct xgbe_ring *tx_ring, *rx_ring;
unsigned int count, i;
DBGPR("-->xgbe_alloc_rings\n");
count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
channel_mem = devm_kcalloc(pdata->dev, count,
sizeof(struct xgbe_channel), GFP_KERNEL);
if (!channel_mem)
return NULL;
tx_ring = devm_kcalloc(pdata->dev, pdata->tx_ring_count,
sizeof(struct xgbe_ring), GFP_KERNEL);
if (!tx_ring)
return NULL;
rx_ring = devm_kcalloc(pdata->dev, pdata->rx_ring_count,
sizeof(struct xgbe_ring), GFP_KERNEL);
if (!rx_ring)
return NULL;
for (i = 0, channel = channel_mem; i < count; i++, channel++) {
snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
channel->pdata = pdata;
channel->queue_index = i;
channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
(DMA_CH_INC * i);
if (i < pdata->tx_ring_count) {
spin_lock_init(&tx_ring->lock);
channel->tx_ring = tx_ring++;
}
if (i < pdata->rx_ring_count) {
spin_lock_init(&rx_ring->lock);
channel->rx_ring = rx_ring++;
}
DBGPR(" %s - queue_index=%u, dma_regs=%p, tx=%p, rx=%p\n",
channel->name, channel->queue_index, channel->dma_regs,
channel->tx_ring, channel->rx_ring);
}
pdata->channel_count = count;
DBGPR("<--xgbe_alloc_rings\n");
return channel_mem;
}
static int tsens_register(struct tsens_device *tmdev)
{
int i, ret;
struct thermal_zone_device *tzd;
u32 *hw_id, n = tmdev->num_sensors;
struct device_node *np = tmdev->dev->of_node;
hw_id = devm_kcalloc(tmdev->dev, n, sizeof(u32), GFP_KERNEL);
if (!hw_id)
return -ENOMEM;
ret = of_property_read_u32_array(np, "qcom,sensor-id", hw_id, n);
for (i = 0; i < tmdev->num_sensors; i++) {
if (ret)
tmdev->sensor[i].hw_id = i;
else
tmdev->sensor[i].hw_id = hw_id[i];
tmdev->sensor[i].tmdev = tmdev;
tmdev->sensor[i].id = i;
tzd = thermal_zone_of_sensor_register(tmdev->dev, i,
&tmdev->sensor[i],
&tsens_of_ops);
if (IS_ERR(tzd))
continue;
tmdev->sensor[i].tzd = tzd;
if (tmdev->ops->enable)
tmdev->ops->enable(tmdev, i);
}
return 0;
}
int rtc_add_groups(struct rtc_device *rtc, const struct attribute_group **grps)
{
size_t old_cnt = 0, add_cnt = 0, new_cnt;
const struct attribute_group **groups, **old;
if (rtc->registered)
return -EINVAL;
if (!grps)
return -EINVAL;
groups = rtc->dev.groups;
if (groups)
for (; *groups; groups++)
old_cnt++;
for (groups = grps; *groups; groups++)
add_cnt++;
new_cnt = old_cnt + add_cnt + 1;
groups = devm_kcalloc(&rtc->dev, new_cnt, sizeof(*groups), GFP_KERNEL);
if (IS_ERR_OR_NULL(groups))
return PTR_ERR(groups);
memcpy(groups, rtc->dev.groups, old_cnt * sizeof(*groups));
memcpy(groups + old_cnt, grps, add_cnt * sizeof(*groups));
groups[old_cnt + add_cnt] = NULL;
old = rtc->dev.groups;
rtc->dev.groups = groups;
if (old && old != rtc_attr_groups)
devm_kfree(&rtc->dev, old);
return 0;
}
static int scmi_clock_protocol_init(struct scmi_handle *handle)
{
u32 version;
int clkid, ret;
struct clock_info *cinfo;
scmi_version_get(handle, SCMI_PROTOCOL_CLOCK, &version);
dev_dbg(handle->dev, "Clock Version %d.%d\n",
PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
cinfo = devm_kzalloc(handle->dev, sizeof(*cinfo), GFP_KERNEL);
if (!cinfo)
return -ENOMEM;
scmi_clock_protocol_attributes_get(handle, cinfo);
cinfo->clk = devm_kcalloc(handle->dev, cinfo->num_clocks,
sizeof(*cinfo->clk), GFP_KERNEL);
if (!cinfo->clk)
return -ENOMEM;
for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
struct scmi_clock_info *clk = cinfo->clk + clkid;
ret = scmi_clock_attributes_get(handle, clkid, clk);
if (!ret)
scmi_clock_describe_rates_get(handle, clkid, clk);
}
handle->clk_ops = &clk_ops;
handle->clk_priv = cinfo;
return 0;
}
int gdsc_register(struct device *dev, struct gdsc **scs, size_t num,
struct reset_controller_dev *rcdev, struct regmap *regmap)
{
int i, ret;
struct genpd_onecell_data *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
GFP_KERNEL);
if (!data->domains)
return -ENOMEM;
data->num_domains = num;
for (i = 0; i < num; i++) {
if (!scs[i])
continue;
scs[i]->regmap = regmap;
scs[i]->rcdev = rcdev;
ret = gdsc_init(scs[i]);
if (ret)
return ret;
data->domains[i] = &scs[i]->pd;
}
return of_genpd_add_provider_onecell(dev->of_node, data);
}
static int gdsc_attach(struct generic_pm_domain *domain, struct device *dev)
{
int ret, i = 0, j = 0;
struct gdsc *sc = domain_to_gdsc(domain);
struct of_phandle_args clkspec;
struct device_node *np = dev->of_node;
if (!sc->clock_count)
return 0;
ret = pm_clk_create(dev);
if (ret) {
dev_dbg(dev, "pm_clk_create failed %d\n", ret);
return ret;
}
sc->clks = devm_kcalloc(dev, sc->clock_count, sizeof(sc->clks),
GFP_KERNEL);
if (!sc->clks)
return -ENOMEM;
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
&clkspec)) {
if (match(clkspec.args[0], sc->clocks, sc->clock_count)) {
sc->clks[j] = of_clk_get_from_provider(&clkspec);
pm_clk_add_clk(dev, sc->clks[j]);
j++;
} else if (clkspec.args[0] == sc->root_clock)
sc->root_clk = of_clk_get_from_provider(&clkspec);
i++;
}
return 0;
};
static int load_one_timing(struct tegra_mc *mc,
struct tegra_mc_timing *timing,
struct device_node *node)
{
int err;
u32 tmp;
err = of_property_read_u32(node, "clock-frequency", &tmp);
if (err) {
dev_err(mc->dev,
"timing %s: failed to read rate\n", node->name);
return err;
}
timing->rate = tmp;
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
sizeof(u32), GFP_KERNEL);
if (!timing->emem_data)
return -ENOMEM;
err = of_property_read_u32_array(node, "nvidia,emem-configuration",
timing->emem_data,
mc->soc->num_emem_regs);
if (err) {
dev_err(mc->dev,
"timing %s: failed to read EMEM configuration\n",
node->name);
return err;
}
return 0;
}
static int scmi_sensors_protocol_init(struct scmi_handle *handle)
{
u32 version;
struct sensors_info *sinfo;
scmi_version_get(handle, SCMI_PROTOCOL_SENSOR, &version);
dev_dbg(handle->dev, "Sensor Version %d.%d\n",
PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
sinfo = devm_kzalloc(handle->dev, sizeof(*sinfo), GFP_KERNEL);
if (!sinfo)
return -ENOMEM;
scmi_sensor_attributes_get(handle, sinfo);
sinfo->sensors = devm_kcalloc(handle->dev, sinfo->num_sensors,
sizeof(*sinfo->sensors), GFP_KERNEL);
if (!sinfo->sensors)
return -ENOMEM;
scmi_sensor_description_get(handle, sinfo);
handle->sensor_ops = &sensor_ops;
handle->sensor_priv = sinfo;
return 0;
}
static int mt76u_alloc_rx(struct mt76_dev *dev)
{
struct mt76_queue *q = &dev->q_rx[MT_RXQ_MAIN];
int i, err, nsgs;
spin_lock_init(&q->rx_page_lock);
spin_lock_init(&q->lock);
q->entry = devm_kcalloc(dev->dev,
MT_NUM_RX_ENTRIES, sizeof(*q->entry),
GFP_KERNEL);
if (!q->entry)
return -ENOMEM;
if (mt76u_check_sg(dev)) {
q->buf_size = MT_RX_BUF_SIZE;
nsgs = MT_SG_MAX_SIZE;
} else {
q->buf_size = PAGE_SIZE;
nsgs = 1;
}
for (i = 0; i < MT_NUM_RX_ENTRIES; i++) {
err = mt76u_buf_alloc(dev, &q->entry[i].ubuf,
nsgs, q->buf_size,
SKB_WITH_OVERHEAD(q->buf_size),
GFP_KERNEL);
if (err < 0)
return err;
}
q->ndesc = MT_NUM_RX_ENTRIES;
return mt76u_submit_rx_buffers(dev);
}
int phy_led_triggers_register(struct phy_device *phy)
{
int i, err;
unsigned int speeds[50];
phy->phy_num_led_triggers = phy_supported_speeds(phy, speeds,
ARRAY_SIZE(speeds));
if (!phy->phy_num_led_triggers)
return 0;
phy->led_link_trigger = devm_kzalloc(&phy->mdio.dev,
sizeof(*phy->led_link_trigger),
GFP_KERNEL);
if (!phy->led_link_trigger) {
err = -ENOMEM;
goto out_clear;
}
phy_led_trigger_format_name(phy, phy->led_link_trigger->name,
sizeof(phy->led_link_trigger->name),
"link");
phy->led_link_trigger->trigger.name = phy->led_link_trigger->name;
err = led_trigger_register(&phy->led_link_trigger->trigger);
if (err)
goto out_free_link;
phy->phy_led_triggers = devm_kcalloc(&phy->mdio.dev,
phy->phy_num_led_triggers,
sizeof(struct phy_led_trigger),
GFP_KERNEL);
if (!phy->phy_led_triggers) {
err = -ENOMEM;
goto out_unreg_link;
}
for (i = 0; i < phy->phy_num_led_triggers; i++) {
err = phy_led_trigger_register(phy, &phy->phy_led_triggers[i],
speeds[i]);
if (err)
goto out_unreg;
}
phy->last_triggered = NULL;
phy_led_trigger_change_speed(phy);
return 0;
out_unreg:
while (i--)
phy_led_trigger_unregister(&phy->phy_led_triggers[i]);
devm_kfree(&phy->mdio.dev, phy->phy_led_triggers);
out_unreg_link:
phy_led_trigger_unregister(phy->led_link_trigger);
out_free_link:
devm_kfree(&phy->mdio.dev, phy->led_link_trigger);
phy->led_link_trigger = NULL;
out_clear:
phy->phy_num_led_triggers = 0;
return err;
}
static int scmi_power_protocol_init(struct scmi_handle *handle)
{
int domain;
u32 version;
struct scmi_power_info *pinfo;
scmi_version_get(handle, SCMI_PROTOCOL_POWER, &version);
dev_dbg(handle->dev, "Power Version %d.%d\n",
PROTOCOL_REV_MAJOR(version), PROTOCOL_REV_MINOR(version));
pinfo = devm_kzalloc(handle->dev, sizeof(*pinfo), GFP_KERNEL);
if (!pinfo)
return -ENOMEM;
scmi_power_attributes_get(handle, pinfo);
pinfo->dom_info = devm_kcalloc(handle->dev, pinfo->num_domains,
sizeof(*pinfo->dom_info), GFP_KERNEL);
if (!pinfo->dom_info)
return -ENOMEM;
for (domain = 0; domain < pinfo->num_domains; domain++) {
struct power_dom_info *dom = pinfo->dom_info + domain;
scmi_power_domain_attributes_get(handle, domain, dom);
}
handle->power_ops = &power_ops;
handle->power_priv = pinfo;
return 0;
}
static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
chip->pins = devm_kcalloc(pfc->dev,
pfc->info->nr_pins, sizeof(*chip->pins),
GFP_KERNEL);
if (chip->pins == NULL)
return -ENOMEM;
ret = gpio_setup_data_regs(chip);
if (ret < 0)
return ret;
gc->request = gpio_pin_request;
gc->free = gpio_pin_free;
gc->direction_input = gpio_pin_direction_input;
gc->get = gpio_pin_get;
gc->direction_output = gpio_pin_direction_output;
gc->set = gpio_pin_set;
gc->to_irq = gpio_pin_to_irq;
gc->label = pfc->info->name;
gc->parent = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
gc->ngpio = pfc->nr_gpio_pins;
return 0;
}
static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
const struct pinmux_data_reg *dreg;
unsigned int i;
/* Count the number of data registers, allocate memory and initialize
* them.
*/
for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
;
chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
GFP_KERNEL);
if (chip->regs == NULL)
return -ENOMEM;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
chip->regs[i].info = dreg;
chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
}
for (i = 0; i < pfc->info->nr_pins; i++) {
if (pfc->info->pins[i].enum_id == 0)
continue;
gpio_setup_data_reg(chip, i);
}
return 0;
}
static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
{
struct cygnus_mux_log *log;
unsigned int i, j;
pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
sizeof(struct cygnus_mux_log),
GFP_KERNEL);
if (!pinctrl->mux_log)
return -ENOMEM;
log = pinctrl->mux_log;
for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
+ j];
log->mux.offset = i * 4;
log->mux.shift = j * 4;
log->mux.alt = 0;
log->is_configured = false;
}
}
return 0;
}
static int simple_parse_aux_devs(struct device_node *node,
struct simple_priv *priv)
{
struct device *dev = simple_priv_to_dev(priv);
struct device_node *aux_node;
struct snd_soc_card *card = simple_priv_to_card(priv);
int i, n, len;
if (!of_find_property(node, PREFIX "aux-devs", &len))
return 0; /* Ok to have no aux-devs */
n = len / sizeof(__be32);
if (n <= 0)
return -EINVAL;
card->aux_dev = devm_kcalloc(dev,
n, sizeof(*card->aux_dev), GFP_KERNEL);
if (!card->aux_dev)
return -ENOMEM;
for (i = 0; i < n; i++) {
aux_node = of_parse_phandle(node, PREFIX "aux-devs", i);
if (!aux_node)
return -EINVAL;
card->aux_dev[i].codec_of_node = aux_node;
}
card->num_aux_devs = n;
return 0;
}
static int as3711_regulator_probe(struct platform_device *pdev)
{
struct as3711_regulator_pdata *pdata = dev_get_platdata(&pdev->dev);
struct as3711 *as3711 = dev_get_drvdata(pdev->dev.parent);
struct regulator_config config = {.dev = &pdev->dev,};
struct as3711_regulator *reg = NULL;
struct as3711_regulator *regs;
struct device_node *of_node[AS3711_REGULATOR_NUM] = {};
struct regulator_dev *rdev;
struct as3711_regulator_info *ri;
int ret;
int id;
if (!pdata) {
dev_err(&pdev->dev, "No platform data...\n");
return -ENODEV;
}
if (pdev->dev.parent->of_node) {
ret = as3711_regulator_parse_dt(&pdev->dev, of_node, AS3711_REGULATOR_NUM);
if (ret < 0) {
dev_err(&pdev->dev, "DT parsing failed: %d\n", ret);
return ret;
}
}
regs = devm_kcalloc(&pdev->dev,
AS3711_REGULATOR_NUM,
sizeof(struct as3711_regulator),
GFP_KERNEL);
if (!regs)
return -ENOMEM;
for (id = 0, ri = as3711_reg_info; id < AS3711_REGULATOR_NUM; ++id, ri++) {
reg = ®s[id];
reg->reg_info = ri;
config.init_data = pdata->init_data[id];
config.driver_data = reg;
config.regmap = as3711->regmap;
config.of_node = of_node[id];
rdev = devm_regulator_register(&pdev->dev, &ri->desc, &config);
if (IS_ERR(rdev)) {
dev_err(&pdev->dev, "Failed to register regulator %s\n",
ri->desc.name);
return PTR_ERR(rdev);
}
}
platform_set_drvdata(pdev, regs);
return 0;
}
static struct platform_driver as3711_regulator_driver = {
.driver = {
.name = "as3711-regulator",
},
.probe = as3711_regulator_probe,
};
static int msm_hdmi_phy_resource_init(struct hdmi_phy *phy)
{
struct hdmi_phy_cfg *cfg = phy->cfg;
struct device *dev = &phy->pdev->dev;
int i, ret;
phy->regs = devm_kcalloc(dev, cfg->num_regs, sizeof(phy->regs[0]),
GFP_KERNEL);
if (!phy->regs)
return -ENOMEM;
phy->clks = devm_kcalloc(dev, cfg->num_clks, sizeof(phy->clks[0]),
GFP_KERNEL);
if (!phy->clks)
return -ENOMEM;
for (i = 0; i < cfg->num_regs; i++) {
struct regulator *reg;
reg = devm_regulator_get(dev, cfg->reg_names[i]);
if (IS_ERR(reg)) {
ret = PTR_ERR(reg);
dev_err(dev, "failed to get phy regulator: %s (%d)\n",
cfg->reg_names[i], ret);
return ret;
}
phy->regs[i] = reg;
}
for (i = 0; i < cfg->num_clks; i++) {
struct clk *clk;
clk = msm_clk_get(phy->pdev, cfg->clk_names[i]);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
dev_err(dev, "failed to get phy clock: %s (%d)\n",
cfg->clk_names[i], ret);
return ret;
}
phy->clks[i] = clk;
}
return 0;
}
int rsnd_mix_probe(struct rsnd_priv *priv)
{
struct device_node *node;
struct device_node *np;
struct device *dev = rsnd_priv_to_dev(priv);
struct rsnd_mix *mix;
struct clk *clk;
char name[MIX_NAME_SIZE];
int i, nr, ret;
/* This driver doesn't support Gen1 at this point */
if (rsnd_is_gen1(priv))
return 0;
node = rsnd_mix_of_node(priv);
if (!node)
return 0; /* not used is not error */
nr = of_get_child_count(node);
if (!nr) {
ret = -EINVAL;
goto rsnd_mix_probe_done;
}
mix = devm_kcalloc(dev, nr, sizeof(*mix), GFP_KERNEL);
if (!mix) {
ret = -ENOMEM;
goto rsnd_mix_probe_done;
}
priv->mix_nr = nr;
priv->mix = mix;
i = 0;
ret = 0;
for_each_child_of_node(node, np) {
mix = rsnd_mix_get(priv, i);
snprintf(name, MIX_NAME_SIZE, "%s.%d",
MIX_NAME, i);
clk = devm_clk_get(dev, name);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
of_node_put(np);
goto rsnd_mix_probe_done;
}
ret = rsnd_mod_init(priv, rsnd_mod_get(mix), &rsnd_mix_ops,
clk, rsnd_mod_get_status, RSND_MOD_MIX, i);
if (ret) {
of_node_put(np);
goto rsnd_mix_probe_done;
}
i++;
}
static int kbase_rk_get_opp_table(struct kbase_device *kbdev)
{
struct kbase_rk *kbase_rk = kbdev->platform_context;
const struct property *prop;
int nr;
const __be32 *val;
int i, start, dir, end;
prop = of_find_property(kbdev->dev->of_node, "operating-points", NULL);
if (!prop)
return -ENODEV;
if (!prop->value)
return -ENODATA;
/*
* Each OPP is a set of tuples consisting of frequency and
* voltage like <freq-kHz vol-uV>.
*/
nr = prop->length / sizeof(u32);
if (nr % 2) {
dev_err(kbdev->dev, "Invalid OPP list\n");
return -EINVAL;
}
kbase_rk->fv_table_length = nr / 2;
kbase_rk->fv_table = devm_kcalloc(kbdev->dev,
kbase_rk->fv_table_length, sizeof(*kbase_rk->fv_table),
GFP_KERNEL);
if (!kbase_rk->fv_table)
return -ENOMEM;
val = prop->value;
/* check the operating-point table start max value or min value */
if ((kbase_rk->fv_table_length > 1) &&
(be32_to_cpup(val) < be32_to_cpup(val + 2))) {
dev_warn(kbdev->dev, "Old backward DVFS table; converting\n");
start = kbase_rk->fv_table_length - 1;
end = 0;
dir = -1;
} else {
start = 0;
end = kbase_rk->fv_table_length - 1;
dir = 1;
}
for (i = start; i != end + dir; i += dir) {
unsigned long freq = be32_to_cpup(val++) * 1000;
unsigned long volt = be32_to_cpup(val++);
kbase_rk->fv_table[i].freq = freq;
kbase_rk->fv_table[i].volt = volt;
dev_info(kbdev->dev, "freq:%lu Hz volt:%lu uV\n", freq, volt);
}
return 0;
}
static int get_mc_addr_translation_ranges(struct device *dev,
struct fsl_mc_addr_translation_range
**ranges,
u8 *num_ranges)
{
int error;
int paddr_cells;
int mc_addr_cells;
int mc_size_cells;
int i;
const __be32 *ranges_start;
const __be32 *cell;
error = parse_mc_ranges(dev,
&paddr_cells,
&mc_addr_cells,
&mc_size_cells,
&ranges_start,
num_ranges);
if (error < 0)
return error;
if (!(*num_ranges)) {
/*
* Missing or empty ranges property ("ranges;") for the
* 'fsl,qoriq-mc' node. In this case, identity mapping
* will be used.
*/
*ranges = NULL;
return 0;
}
*ranges = devm_kcalloc(dev, *num_ranges,
sizeof(struct fsl_mc_addr_translation_range),
GFP_KERNEL);
if (!(*ranges))
return -ENOMEM;
cell = ranges_start;
for (i = 0; i < *num_ranges; ++i) {
struct fsl_mc_addr_translation_range *range = &(*ranges)[i];
range->mc_region_type = of_read_number(cell, 1);
range->start_mc_offset = of_read_number(cell + 1,
mc_addr_cells - 1);
cell += mc_addr_cells;
range->start_phys_addr = of_read_number(cell, paddr_cells);
cell += paddr_cells;
range->end_mc_offset = range->start_mc_offset +
of_read_number(cell, mc_size_cells);
cell += mc_size_cells;
}
return 0;
}
static int rk808_clkout_probe(struct platform_device *pdev)
{
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
struct i2c_client *client = rk808->i2c;
struct device_node *node = client->dev.of_node;
struct clk_init_data init = {};
struct clk **clk_table;
struct rk808_clkout *rk808_clkout;
rk808_clkout = devm_kzalloc(&client->dev,
sizeof(*rk808_clkout), GFP_KERNEL);
if (!rk808_clkout)
return -ENOMEM;
rk808_clkout->rk808 = rk808;
clk_table = devm_kcalloc(&client->dev, RK808_NR_OUTPUT,
sizeof(struct clk *), GFP_KERNEL);
if (!clk_table)
return -ENOMEM;
init.parent_names = NULL;
init.num_parents = 0;
init.name = "rk808-clkout1";
init.ops = &rk808_clkout1_ops;
rk808_clkout->clkout1_hw.init = &init;
/* optional override of the clockname */
of_property_read_string_index(node, "clock-output-names",
0, &init.name);
clk_table[0] = devm_clk_register(&client->dev,
&rk808_clkout->clkout1_hw);
if (IS_ERR(clk_table[0]))
return PTR_ERR(clk_table[0]);
init.name = "rk808-clkout2";
init.ops = &rk808_clkout2_ops;
rk808_clkout->clkout2_hw.init = &init;
/* optional override of the clockname */
of_property_read_string_index(node, "clock-output-names",
1, &init.name);
clk_table[1] = devm_clk_register(&client->dev,
&rk808_clkout->clkout2_hw);
if (IS_ERR(clk_table[1]))
return PTR_ERR(clk_table[1]);
rk808_clkout->clk_data.clks = clk_table;
rk808_clkout->clk_data.clk_num = RK808_NR_OUTPUT;
return of_clk_add_provider(node, of_clk_src_onecell_get,
&rk808_clkout->clk_data);
}
static int of_get_max1586_platform_data(struct device *dev,
struct max1586_platform_data *pdata)
{
struct max1586_subdev_data *sub;
struct of_regulator_match rmatch[ARRAY_SIZE(max1586_reg)] = { };
struct device_node *np = dev->of_node;
int i, matched;
if (of_property_read_u32(np, "v3-gain",
&pdata->v3_gain) < 0) {
dev_err(dev, "%pOF has no 'v3-gain' property\n", np);
return -EINVAL;
}
np = of_get_child_by_name(np, "regulators");
if (!np) {
dev_err(dev, "missing 'regulators' subnode in DT\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(rmatch); i++)
rmatch[i].name = max1586_reg[i].name;
matched = of_regulator_match(dev, np, rmatch, ARRAY_SIZE(rmatch));
of_node_put(np);
/*
* If matched is 0, ie. neither Output_V3 nor Output_V6 have been found,
* return 0, which signals the normal situation where no subregulator is
* available. This is normal because the max1586 doesn't provide any
* readback support, so the subregulators can't report any status
* anyway. If matched < 0, return the error.
*/
if (matched <= 0)
return matched;
pdata->subdevs = devm_kcalloc(dev,
matched,
sizeof(struct max1586_subdev_data),
GFP_KERNEL);
if (!pdata->subdevs)
return -ENOMEM;
pdata->num_subdevs = matched;
sub = pdata->subdevs;
for (i = 0; i < matched; i++) {
sub->id = i;
sub->name = rmatch[i].of_node->name;
sub->platform_data = rmatch[i].init_data;
sub++;
}
return 0;
}
static int hisi_femac_init_queue(struct device *dev,
struct hisi_femac_queue *queue,
unsigned int num)
{
queue->skb = devm_kcalloc(dev, num, sizeof(struct sk_buff *),
GFP_KERNEL);
if (!queue->skb)
return -ENOMEM;
queue->dma_phys = devm_kcalloc(dev, num, sizeof(dma_addr_t),
GFP_KERNEL);
if (!queue->dma_phys)
return -ENOMEM;
queue->num = num;
queue->head = 0;
queue->tail = 0;
return 0;
}
static int
mt76_init_sband(struct mt76_dev *dev, struct mt76_sband *msband,
const struct ieee80211_channel *chan, int n_chan,
struct ieee80211_rate *rates, int n_rates, bool vht)
{
struct ieee80211_supported_band *sband = &msband->sband;
struct ieee80211_sta_ht_cap *ht_cap;
struct ieee80211_sta_vht_cap *vht_cap;
void *chanlist;
int size;
size = n_chan * sizeof(*chan);
chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
if (!chanlist)
return -ENOMEM;
msband->chan = devm_kcalloc(dev->dev, n_chan, sizeof(*msband->chan),
GFP_KERNEL);
if (!msband->chan)
return -ENOMEM;
sband->channels = chanlist;
sband->n_channels = n_chan;
sband->bitrates = rates;
sband->n_bitrates = n_rates;
dev->chandef.chan = &sband->channels[0];
ht_cap = &sband->ht_cap;
ht_cap->ht_supported = true;
ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
IEEE80211_HT_CAP_GRN_FLD |
IEEE80211_HT_CAP_SGI_20 |
IEEE80211_HT_CAP_SGI_40 |
(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
mt76_init_stream_cap(dev, sband, vht);
if (!vht)
return 0;
vht_cap = &sband->vht_cap;
vht_cap->vht_supported = true;
vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC |
IEEE80211_VHT_CAP_RXSTBC_1 |
IEEE80211_VHT_CAP_SHORT_GI_80 |
(3 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT);
return 0;
}
static int mt7601u_alloc_tx(struct mt7601u_dev *dev)
{
int i;
dev->tx_q = devm_kcalloc(dev->dev, __MT_EP_OUT_MAX,
sizeof(*dev->tx_q), GFP_KERNEL);
for (i = 0; i < __MT_EP_OUT_MAX; i++)
if (mt7601u_alloc_tx_queue(dev, &dev->tx_q[i]))
return -ENOMEM;
return 0;
}
static int syscfg_reset_controller_register(struct device *dev,
const struct syscfg_reset_controller_data *data)
{
struct syscfg_reset_controller *rc;
int i, err;
rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
if (!rc)
return -ENOMEM;
rc->channels = devm_kcalloc(dev, data->nr_channels,
sizeof(*rc->channels), GFP_KERNEL);
if (!rc->channels)
return -ENOMEM;
rc->rst.ops = &syscfg_reset_ops,
rc->rst.of_node = dev->of_node;
rc->rst.nr_resets = data->nr_channels;
rc->active_low = data->active_low;
for (i = 0; i < data->nr_channels; i++) {
struct regmap *map;
struct regmap_field *f;
const char *compatible = data->channels[i].compatible;
map = syscon_regmap_lookup_by_compatible(compatible);
if (IS_ERR(map))
return PTR_ERR(map);
f = devm_regmap_field_alloc(dev, map, data->channels[i].reset);
if (IS_ERR(f))
return PTR_ERR(f);
rc->channels[i].reset = f;
if (!data->wait_for_ack)
continue;
f = devm_regmap_field_alloc(dev, map, data->channels[i].ack);
if (IS_ERR(f))
return PTR_ERR(f);
rc->channels[i].ack = f;
}
err = reset_controller_register(&rc->rst);
if (!err)
dev_info(dev, "registered\n");
return err;
}
static int gpio_dwapb_bind(struct udevice *dev)
{
struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
struct udevice *subdev;
fdt_addr_t base;
int ret, bank = 0;
ofnode node;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
for (node = dev_read_first_subnode(dev); ofnode_valid(node);
node = dev_read_next_subnode(node)) {
if (!ofnode_read_bool(node, "gpio-controller"))
continue;
plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
if (!plat)
return -ENOMEM;
plat->base = base;
plat->bank = bank;
plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
/*
* Fall back to node name. This means accessing pins
* via bank name won't work.
*/
plat->name = ofnode_get_name(node);
}
ret = device_bind(dev, dev->driver, plat->name,
plat, -1, &subdev);
if (ret)
return ret;
dev->node = node;
bank++;
}
return 0;
}
static int pm8xxx_xoadc_parse_channels(struct pm8xxx_xoadc *adc,
struct device_node *np)
{
struct device_node *child;
struct pm8xxx_chan_info *ch;
int ret;
int i;
adc->nchans = of_get_available_child_count(np);
if (!adc->nchans) {
dev_err(adc->dev, "no channel children\n");
return -ENODEV;
}
dev_dbg(adc->dev, "found %d ADC channels\n", adc->nchans);
adc->iio_chans = devm_kcalloc(adc->dev, adc->nchans,
sizeof(*adc->iio_chans), GFP_KERNEL);
if (!adc->iio_chans)
return -ENOMEM;
adc->chans = devm_kcalloc(adc->dev, adc->nchans,
sizeof(*adc->chans), GFP_KERNEL);
if (!adc->chans)
return -ENOMEM;
i = 0;
for_each_available_child_of_node(np, child) {
ch = &adc->chans[i];
ret = pm8xxx_xoadc_parse_channel(adc->dev, child,
adc->variant->channels,
&adc->iio_chans[i],
ch);
if (ret) {
of_node_put(child);
return ret;
}
i++;
}
/*
* Create a default correction table for PWM values to create linear brightness
* for LED based backlights using the CIE1931 algorithm.
*/
static
int pwm_backlight_brightness_default(struct device *dev,
struct platform_pwm_backlight_data *data,
unsigned int period)
{
unsigned int counter = 0;
unsigned int i, n;
u64 retval;
/*
* Count the number of bits needed to represent the period number. The
* number of bits is used to calculate the number of levels used for the
* brightness-levels table, the purpose of this calculation is have a
* pre-computed table with enough levels to get linear brightness
* perception. The period is divided by the number of bits so for a
* 8-bit PWM we have 255 / 8 = 32 brightness levels or for a 16-bit PWM
* we have 65535 / 16 = 4096 brightness levels.
*
* Note that this method is based on empirical testing on different
* devices with PWM of 8 and 16 bits of resolution.
*/
n = period;
while (n) {
counter += n % 2;
n >>= 1;
}
data->max_brightness = DIV_ROUND_UP(period, counter);
data->levels = devm_kcalloc(dev, data->max_brightness,
sizeof(*data->levels), GFP_KERNEL);
if (!data->levels)
return -ENOMEM;
/* Fill the table using the cie1931 algorithm */
for (i = 0; i < data->max_brightness; i++) {
retval = cie1931((i * PWM_LUMINANCE_SCALE) /
data->max_brightness, PWM_LUMINANCE_SCALE) *
period;
retval = DIV_ROUND_CLOSEST_ULL(retval, PWM_LUMINANCE_SCALE);
if (retval > UINT_MAX)
return -EINVAL;
data->levels[i] = (unsigned int)retval;
}
data->dft_brightness = data->max_brightness / 2;
data->max_brightness--;
return 0;
}