void
MODSERIAL::init( int txSize, int rxSize, PinName rx )
{
disableIrq();
callbackInfo.setSerial(this);
#ifdef __LPC11UXX_H__
_base = LPC_USART;
#else
switch( _serial.index ) {
case 0: _base = LPC_UART0; break;
case 1: _base = LPC_UART1; break;
case 2: _base = LPC_UART2; break;
case 3: _base = LPC_UART3; break;
default: _base = NULL; break;
}
#endif
dmaSendChannel = -1;
moddma_p = (void *)NULL;
if ( _base != NULL ) {
buffer_size[RxIrq] = rxSize;
buffer[RxIrq] = rxSize > 0 ? (char *)malloc(buffer_size[RxIrq]) : (char *)NULL;
buffer_in[RxIrq] = 0;
buffer_out[RxIrq] = 0;
buffer_count[RxIrq] = 0;
buffer_overflow[RxIrq] = 0;
Serial::attach( this, &MODSERIAL::isr_rx, Serial::RxIrq );
buffer_size[TxIrq] = txSize;
buffer[TxIrq] = txSize > 0 ? (char *)malloc(buffer_size[TxIrq]) : (char *)NULL;
buffer_in[TxIrq] = 0;
buffer_out[TxIrq] = 0;
buffer_count[TxIrq] = 0;
buffer_overflow[TxIrq] = 0;
Serial::attach( this, &MODSERIAL::isr_tx, Serial::TxIrq );
}
else {
error("MODSERIAL must have a defined UART to function.");
}
_FCR = MODSERIAL_FIFO_ENABLE | MODSERIAL_FIFO_RX_RESET | MODSERIAL_FIFO_TX_RESET;
auto_detect_char = 0;
enableIrq();
}
MODSERIAL::~MODSERIAL()
{
disableIrq();
if (buffer[0] != NULL) free((char *)buffer[0]);
if (buffer[1] != NULL) free((char *)buffer[1]);
}
void initMainHardware(void)
{
disableIrq(); /* Ensure INTC current prority=0 & enable IRQ */
initBTB();
initModesAndClock();
initPeriClkGen() ;
initPads ();
disableWatchdog();
init_LinFLEX_0_UART ();
initCAN_1(); /* Initialize FLEXCAN 0*/
initSBC(); //init SBC for CAN
initADC();
initINTC(); /* Initialize INTC for software vector mode */
initPIT(); /* Initialize PIT1 for 1KHz IRQ, priority 2 */
// initSwIrq4(); /* Initialize software interrupt 4 */
SIU.PSMI[0].R = 1; //can1rxd=43
SIU.PSMI[7].R = 2; //dspi1_sscl=114
SIU.PSMI[8].R = 2; //dspi1_sscl=114
SIU.PSMI[9].R = 3; //dspi1_sscl=114
EMIOS_0.MCR.B.GPRE= 63; /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/
EMIOS_0.MCR.B.GPREN = 1; /* Enable eMIOS clock */
EMIOS_0.MCR.B.GTBE = 1; /* Enable global time base */
EMIOS_0.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */
EMIOS_0.CH[0].CADR.R = 14999; /* Period will be 19999+1 = 20000 clocks (20 msec)*/
EMIOS_0.CH[0].CCR.B.MODE = 0x50; /* Modulus Counter Buffered (MCB) */
EMIOS_0.CH[0].CCR.B.BSL = 0x3; /* Use internal counter */
EMIOS_0.CH[0].CCR.B.UCPRE=0; /* Set channel prescaler to divide by 1 */
EMIOS_0.CH[0].CCR.B.UCPEN = 1; /* Enable prescaler; uses default divide by 1*/
EMIOS_0.CH[0].CCR.B.FREN = 1; /* Freeze channel counting when in debug mode*/
EMIOS_0.CH[23].CADR.R = 999; /* Period will be 999+1 = 1000 clocks (1 msec)*/
EMIOS_0.CH[23].CCR.B.MODE = 0x50; /* Modulus Counter Buffered (MCB) */
EMIOS_0.CH[23].CCR.B.BSL = 0x3; /* Use internal counter */
EMIOS_0.CH[23].CCR.B.UCPRE=0; /* Set channel prescaler to divide by 1 */
EMIOS_0.CH[23].CCR.B.UCPEN = 1; /* Enable prescaler; uses default divide by 1*/
EMIOS_0.CH[23].CCR.B.FREN = 1; /* Freeze channel counting when in debug mode*/
EMIOS_0.CH[4].CADR.R = 0; /* Leading edge when channel counter bus=0*/
EMIOS_0.CH[4].CBDR.R = 1500; /* Trailing edge when channel counter bus=1400 Middle, 1650 Right Max, 1150 Left Max*/
EMIOS_0.CH[4].CCR.B.BSL = 0x01; /* Use counter bus B */
EMIOS_0.CH[4].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output */
EMIOS_0.CH[4].CCR.B.MODE = 0x60; /* Mode is OPWM Buffered */
SIU.PCR[28].R = 0x0600; /* MPC56xxS: Assign EMIOS_0 ch 6 to pad */
EMIOS_0.CH[6].CADR.R = 000; /* Leading edge when channel counter bus=0*/
EMIOS_0.CH[6].CBDR.R = 950; /* Trailing edge when channel counter bus=500*/
EMIOS_0.CH[6].CCR.B.BSL = 0x0; /* Use counter bus A (default) */
EMIOS_0.CH[6].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output */
EMIOS_0.CH[6].CCR.B.MODE = 0x60; /* Mode is OPWM Buffered */
SIU.PCR[30].R = 0x0600; /* MPC56xxS: Assign EMIOS_0 ch 6 to pad */
EMIOS_0.CH[7].CADR.R = 0; /* Leading edge when channel counter bus=0*/
EMIOS_0.CH[7].CBDR.R = 950; /* Trailing edge when channel's counter bus=999*/
EMIOS_0.CH[7].CCR.B.BSL = 0x0; /* Use counter bus A (default) */
EMIOS_0.CH[7].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output*/
EMIOS_0.CH[7].CCR.B.MODE = 0x60; /* Mode is OPWM Buffered */
SIU.PCR[31].R = 0x0600; /* MPC56xxS: Assign EMIOS_0 ch 7 to pad */
EMIOS_0.CH[3].CADR.R = 250; /* Ch 3: Match "A" is 250 */
EMIOS_0.CH[3].CBDR.R = 500; /* Ch 3: Match "B" is 500 */
EMIOS_0.CH[3].CCR.R= 0x000000E0; /* Ch 3: Mode is OPWMB, time base = ch 23 */
EMIOS_0.CH[2].CCR.R= 0x01020082; /* Ch 2: Mode is SAIC, time base = ch 23 */
SIU.PCR[17].R = 0x0200; /* Program the drive enable pin of Right Motor as output*/
SIU.PCR[16].R = 0x0200; /* Program the drive enable pin of Left Motor as output*/
SIU.PGPDO[0].R = 0x00000000; /* Disable the motors */
INTC.CPR.B.PRI = 0; /* Single Core: Lower INTC's current priority */
asm(" wrteei 1"); /* Enable external interrupts */
}
