/** * @brief Deactivates the SPI peripheral. * * @param[in] spip pointer to the @p SPIDriver object * * @notapi */ void spi_lld_stop(SPIDriver *spip) { /* If in ready state then disables the SPI clock.*/ if (spip->state == SPI_READY) { /* SPI disable.*/ spip->spi->CR1 = 0; spip->spi->CR2 = 0; dmaStreamRelease(spip->dmarx); dmaStreamRelease(spip->dmatx); #if STM32_SPI_USE_SPI1 if (&SPID1 == spip) rccDisableSPI1(FALSE); #endif #if STM32_SPI_USE_SPI2 if (&SPID2 == spip) rccDisableSPI2(FALSE); #endif #if STM32_SPI_USE_SPI3 if (&SPID3 == spip) rccDisableSPI3(FALSE); #endif } }
/** * @brief Deactivates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object * * @notapi */ void i2c_lld_stop(I2CDriver *i2cp) { /* If not in stopped state then disables the I2C clock.*/ if (i2cp->state != I2C_STOP) { /* I2C disable.*/ i2c_lld_abort_operation(i2cp); dmaStreamRelease(i2cp->dmatx); dmaStreamRelease(i2cp->dmarx); #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { nvicDisableVector(I2C1_EV_IRQn); nvicDisableVector(I2C1_ER_IRQn); rccDisableI2C1(FALSE); } #endif #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { nvicDisableVector(I2C2_EV_IRQn); nvicDisableVector(I2C2_ER_IRQn); rccDisableI2C2(FALSE); } #endif #if STM32_I2C_USE_I2C3 if (&I2CD3 == i2cp) { nvicDisableVector(I2C3_EV_IRQn); nvicDisableVector(I2C3_ER_IRQn); rccDisableI2C3(FALSE); } #endif } }
/** * @brief Deactivates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_stop(UARTDriver *uartp) { if (uartp->state == UART_READY) { usart_stop(uartp); dmaStreamRelease(uartp->dmarx); dmaStreamRelease(uartp->dmatx); #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { nvicDisableVector(STM32_USART1_NUMBER); rccDisableUSART1(FALSE); return; } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { nvicDisableVector(STM32_USART2_NUMBER); rccDisableUSART2(FALSE); return; } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { nvicDisableVector(STM32_USART3_NUMBER); rccDisableUSART3(FALSE); return; } #endif } }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock and analog part.*/ if (adcp->state == ADC_READY) { /* Releasing the associated DMA channel.*/ dmaStreamRelease(adcp->dmastp); /* Stopping the ongoing conversion, if any.*/ adc_lld_stop_adc(adcp); /* Disabling ADC analog circuit and regulator.*/ adc_lld_analog_off(adcp); adc_lld_vreg_off(adcp); #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) rccDisableADC12(FALSE); #endif #if STM32_ADC_USE_ADC3 if (&ADCD3 == adcp) rccDisableADC34(FALSE); #endif } }
void gpdrive_deinit(void) { if (!m_init_done) { return; } m_init_done = false; timer_thd_stop = true; while (timer_thd_stop) { chThdSleepMilliseconds(1); } TIM_DeInit(TIM1); TIM_DeInit(TIM12); ADC_DeInit(); DMA_DeInit(DMA2_Stream4); nvicDisableVector(ADC_IRQn); dmaStreamRelease(STM32_DMA_STREAM(STM32_DMA_STREAM_ID(2, 4))); // Restore pins palSetPadMode(GPIOA, 9, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUDR_FLOATING); palSetPadMode(GPIOB, 14, PAL_MODE_ALTERNATE(GPIO_AF_TIM1) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUDR_FLOATING); }
/** * @brief Deactivates the SDC peripheral. * * @param[in] sdcp pointer to the @p SDCDriver object * * @notapi */ void sdc_lld_stop(SDCDriver *sdcp) { if (sdcp->state != BLK_STOP) { /* SDIO deactivation.*/ sdcp->sdmmc->POWER = 0; sdcp->sdmmc->CLKCR = 0; sdcp->sdmmc->DCTRL = 0; sdcp->sdmmc->DTIMER = 0; /* DMA stream released.*/ dmaStreamRelease(sdcp->dma); /* Clock deactivation.*/ #if STM32_SDC_USE_SDMMC1 if (&SDCD1 == sdcp) { rccDisableSDMMC1(FALSE); } #endif #if STM32_SDC_USE_SDMMC2 if (&SDCD2 == sdcp) { rccDisableSDMMC2(FALSE); } #endif } }
/** * @brief Deactivates the DAC peripheral. * * @param[in] dacp pointer to the @p DACDriver object * * @notapi */ void dac_lld_stop(DACDriver *dacp) { /* If in ready state then disables the DAC clock.*/ if (dacp->state == DAC_READY) { /* DMA disable.*/ dmaStreamRelease(dacp->dma); #if STM32_DAC_USE_CHN1 if (&DACD1 == dacp) { dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC1 disable.*/ } #endif #if STM32_DAC_USE_CHN2 if (&DACD2 == dacp) { dacp->dac->CR &= ~STM32_DAC_CR_EN << 16; /* DAC1 disable.*/ } #endif #if STM32_DAC_USE_CHN3 if (&DACD3 == dacp) { dacp->dac->CR &= ~STM32_DAC_CR_EN; /* DAC2 disable.*/ rccDisableDAC2(FALSE); /* DAC Clock disable.*/ } #endif dacp->tim->CR1 &= ~TIM_CR1_CEN; /* Disable associated timer */ dacp->state = DAC_STOP; if (!(DAC1->CR & (STM32_DAC_CR_EN | STM32_DAC_CR_EN << 16))) { /* DAC Clock disable only if all channels are off.*/ rccDisableDAC1(FALSE); } } }
/** * @brief Deactivates the CRC peripheral. * * @param[in] crcp pointer to the @p CRCDriver object * * @notapi */ void crc_lld_stop(CRCDriver *crcp) { #if CRC_USE_DMA == TRUE dmaStreamRelease(crcp->dma); #else (void)crcp; #endif rccDisableCRC(FALSE); }
/** * @brief Deactivates the NAND peripheral. * * @param[in] nandp pointer to the @p NANDDriver object * * @notapi */ void nand_lld_stop(NANDDriver *nandp) { if (nandp->state == NAND_READY) { dmaStreamRelease(nandp->dma); nandp->nand->PCR &= ~FSMC_PCR_PBKEN; nand_ready_isr_disable(nandp); nandp->isr_handler = NULL; } }
/** * @brief Deactivates the I2C peripheral. * * @param[in] i2cp pointer to the @p I2CDriver object * * @notapi */ void i2c_lld_stop(I2CDriver *i2cp) { /* If not in stopped state then disables the I2C clock.*/ if (i2cp->state != I2C_STOP) { /* I2C disable.*/ i2c_lld_abort_operation(i2cp); #if STM32_I2C_USE_DMA == TRUE dmaStreamRelease(i2cp->dmatx); dmaStreamRelease(i2cp->dmarx); #endif #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { #if defined(STM32_I2C1_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicDisableVector(STM32_I2C1_GLOBAL_NUMBER); #elif defined(STM32_I2C1_EVENT_NUMBER) && defined(STM32_I2C1_ERROR_NUMBER) nvicDisableVector(STM32_I2C1_EVENT_NUMBER); nvicDisableVector(STM32_I2C1_ERROR_NUMBER); #else #error "I2C1 interrupt numbers not defined" #endif rccDisableI2C1(FALSE); } #endif #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { #if defined(STM32_I2C2_GLOBAL_NUMBER) || defined(__DOXYGEN__) nvicDisableVector(STM32_I2C2_GLOBAL_NUMBER); #elif defined(STM32_I2C2_EVENT_NUMBER) && defined(STM32_I2C2_ERROR_NUMBER) nvicDisableVector(STM32_I2C2_EVENT_NUMBER); nvicDisableVector(STM32_I2C2_ERROR_NUMBER); #else #error "I2C2 interrupt numbers not defined" #endif rccDisableI2C2(FALSE); } #endif } }
/** * @brief Deactivates the I2S peripheral. * * @param[in] i2sp pointer to the @p I2SDriver object * * @notapi */ void i2s_lld_stop(I2SDriver *i2sp) { /* If in ready state then disables the SPI clock.*/ if (i2sp->state == I2S_READY) { /* SPI disable.*/ i2sp->spi->CR2 = 0; if (NULL != i2sp->dmarx) dmaStreamRelease(i2sp->dmarx); if (NULL != i2sp->dmatx) dmaStreamRelease(i2sp->dmatx); #if STM32_I2S_USE_SPI2 if (&I2SD2 == i2sp) rccDisableSPI2(FALSE); #endif #if STM32_I2S_USE_SPI3 if (&I2SD3 == i2sp) rccDisableSPI3(FALSE); #endif } }
/** * @brief Deactivates the SDC peripheral. * * @param[in] sdcp pointer to the @p SDCDriver object * * @notapi */ void sdc_lld_stop(SDCDriver *sdcp) { if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { SDIO->POWER = 0; SDIO->CLKCR = 0; SDIO->DCTRL = 0; SDIO->DTIMER = 0; /* Clock deactivation.*/ nvicDisableVector(SDIO_IRQn); dmaStreamRelease(STM32_DMA2_STREAM4); rccDisableSDIO(FALSE); } }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock.*/ if (adcp->state == ADC_READY) { #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { ADC1->CR1 = 0; ADC1->CR2 = 0; dmaStreamRelease(adcp->dmastp); rccDisableADC1(FALSE); } #endif } }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock and analog part.*/ if (adcp->state == ADC_READY) { dmaStreamRelease(adcp->dmastp); adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) rccDisableADC1(FALSE); #endif } }
*/ void sdc_lld_stop(SDCDriver *sdcp) { if (sdcp->state != BLK_STOP) { /* SDIO deactivation.*/ SDIO->POWER = 0; SDIO->CLKCR = 0; SDIO->DCTRL = 0; SDIO->DTIMER = 0; /* Clock deactivation.*/ nvicDisableVector(STM32_SDIO_NUMBER); dmaStreamRelease(sdcp->dma); rccDisableSDIO(FALSE); }
/** * @brief Deactivates the QSPI peripheral. * * @param[in] qspip pointer to the @p QSPIDriver object * * @notapi */ void qspi_lld_stop(QSPIDriver *qspip) { /* If in ready state then disables the QUADSPI clock.*/ if (qspip->state == QSPI_READY) { /* QSPI disable.*/ qspip->qspi->CR = 0U; /* Releasing the DMA.*/ dmaStreamRelease(qspip->dma); /* Stopping involved clocks.*/ #if STM32_QSPI_USE_QUADSPI1 if (&QSPID1 == qspip) { rccDisableQUADSPI1(FALSE); } #endif } }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock.*/ if (adcp->state == ADC_READY) { dmaStreamRelease(adcp->dmastp); #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; rccDisableADC1(FALSE); } #endif #if STM32_ADC_USE_SDADC1 if (&SDADCD1 == adcp) { adcp->sdadc->CR1 = 0; adcp->sdadc->CR2 = 0; rccDisableSDADC1(FALSE); PWR->CR &= ~PWR_CR_SDADC1EN; } #endif #if STM32_ADC_USE_SDADC2 if (&SDADCD2 == adcp) { adcp->sdadc->CR1 = 0; adcp->sdadc->CR2 = 0; rccDisableSDADC2(FALSE); PWR->CR &= ~PWR_CR_SDADC2EN; } #endif #if STM32_ADC_USE_SDADC3 if (&SDADCD3 == adcp) { adcp->sdadc->CR1 = 0; adcp->sdadc->CR2 = 0; rccDisableSDADC3(FALSE); PWR->CR &= ~PWR_CR_SDADC3EN; } #endif } }
/** * @brief Stops an ongoing conversion. * @details This function stops the currently ongoing conversion and returns * the driver in the @p DAC_READY state. If there was no conversion * being processed then the function does nothing. * * @param[in] dacp pointer to the @p DACDriver object * * @iclass */ void dac_lld_stop_conversion(DACDriver *dacp) { /* DMA channel disabled and released.*/ dmaStreamDisable(dacp->params->dma); dmaStreamRelease(dacp->params->dma); #if STM32_DAC_DUAL_MODE == FALSE dacp->params->dac->CR &= dacp->params->regmask; dacp->params->dac->CR |= DAC_CR_EN1 << dacp->params->regshift; #else if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) || (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) || (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) { dacp->params->dac->CR = DAC_CR_EN2 | DAC_CR_EN1; } else { dacp->params->dac->CR = DAC_CR_EN1; } #endif }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock and analog part.*/ if (adcp->state == ADC_READY) { dmaStreamRelease(adcp->dmastp); /* Disabling ADC.*/ if (adcp->adc->CR & ADC_CR_ADEN) { adc_lld_stop_adc(adcp->adc); adcp->adc->CR |= ADC_CR_ADDIS; while (adcp->adc->CR & ADC_CR_ADDIS) ; } #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) rccDisableADC1(FALSE); #endif } }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock.*/ if (adcp->state == ADC_READY) { dmaStreamRelease(adcp->dmastp); adcp->adc->CR1 = 0; adcp->adc->CR2 = 0; #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) rccDisableADC1(); #endif #if STM32_ADC_USE_ADC2 if (&ADCD2 == adcp) rccDisableADC2(); #endif #if STM32_ADC_USE_ADC3 if (&ADCD3 == adcp) rccDisableADC3(); #endif } }
void Adc_t::Disable() { ADC1->CR2 = 0; dmaStreamRelease(ADC_DMA); }
void Adc_t::Disable() { ADC1->CR2 = 0; dmaStreamRelease(ADC_DMA); rccDisableADC1(FALSE); }
/** * @brief Deactivates the ADC peripheral. * * @param[in] adcp pointer to the @p ADCDriver object * * @notapi */ void adc_lld_stop(ADCDriver *adcp) { /* If in ready state then disables the ADC clock and analog part.*/ if (adcp->state == ADC_READY) { /* Releasing the associated DMA channel.*/ dmaStreamRelease(adcp->dmastp); /* Stopping the ongoing conversion, if any.*/ adc_lld_stop_adc(adcp); /* Disabling ADC analog circuit and regulator.*/ adc_lld_analog_off(adcp); adc_lld_vreg_off(adcp); #if defined(STM32L4XX) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA; #endif #if STM32_ADC_USE_ADC1 if (&ADCD1 == adcp) { #if defined(STM32F3XX) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; #endif clkmask &= ~(1 << 0); } #endif #if STM32_ADC_USE_ADC2 if (&ADCD2 == adcp) { #if defined(STM32F3XX) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA; #endif clkmask &= ~(1 << 1); } #endif #if STM32_ADC_USE_ADC3 if (&ADCD3 == adcp) { #if defined(STM32F3XX) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; #endif clkmask &= ~(1 << 2); } #endif #if STM32_ADC_USE_ADC4 if (&ADCD4 == adcp) { #if defined(STM32F3XX) /* Resetting CCR options except default ones.*/ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA; #endif clkmask &= ~(1 << 3); } #endif #if defined(STM32F3XX) #if STM32_HAS_ADC1 || STM32_HAS_ADC2 if ((clkmask & 0x3) == 0) { rccDisableADC12(FALSE); } #endif #if STM32_HAS_ADC3 || STM32_HAS_ADC4 if ((clkmask & 0xC) == 0) { rccDisableADC34(FALSE); } #endif #endif #if defined(STM32L4XX) if ((clkmask & 0x7) == 0) { rccDisableADC123(FALSE); } #endif } }
/** * @brief Deactivates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_stop(UARTDriver *uartp) { if (uartp->state == UART_READY) { usart_stop(uartp); dmaStreamRelease(uartp->dmarx); dmaStreamRelease(uartp->dmatx); #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { nvicDisableVector(STM32_USART1_NUMBER); rccDisableUSART1(FALSE); return; } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { nvicDisableVector(STM32_USART2_NUMBER); rccDisableUSART2(FALSE); return; } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { nvicDisableVector(STM32_USART3_NUMBER); rccDisableUSART3(FALSE); return; } #endif #if STM32_UART_USE_UART4 if (&UARTD4 == uartp) { nvicDisableVector(STM32_UART4_NUMBER); rccDisableUART4(FALSE); return; } #endif #if STM32_UART_USE_UART5 if (&UARTD5 == uartp) { nvicDisableVector(STM32_UART5_NUMBER); rccDisableUART5(FALSE); return; } #endif #if STM32_UART_USE_USART6 if (&UARTD6 == uartp) { nvicDisableVector(STM32_USART6_NUMBER); rccDisableUSART6(FALSE); return; } #endif #if STM32_UART_USE_UART7 if (&UARTD7 == uartp) { nvicDisableVector(STM32_UART7_NUMBER); rccDisableUART7(FALSE); return; } #endif #if STM32_UART_USE_UART8 if (&UARTD8 == uartp) { nvicDisableVector(STM32_UART8_NUMBER); rccDisableUART8(FALSE); return; } #endif } }