/* This function is called in dma intr handler (DMA RCV_INT interrupt). * This function get the data from the DMA device. */ static void switch_hw_receive(struct dma_device_info* dma_dev) { unsigned char* buf=NULL; int len=0 ; struct sk_buff *skb=NULL; struct net_device *dev; len = dma_device_read(dma_dev,&buf,(void**)&skb); if ((len >= 0x600) || (len < 64) ) { printk(KERN_ERR "%s[%d]: Packet is too large/small (%d)!!!\n", __func__,__LINE__,len); goto rx_err_exit; } if (skb == NULL ) { printk(KERN_ERR "%s[%d]: Can't restore the Packet !!!\n", __func__,__LINE__); goto rx_err_exit; } /* remove CRC */ len -= 4; if (len > (skb->end -skb->tail)) { printk(KERN_ERR "%s[%d]: len:%d end:%p tail:%p Err!!!\n", __func__,__LINE__,(len+4), skb->end, skb->tail); goto rx_err_exit; } skb_put(skb,len); dev= ifx_eth_dev[0]; skb->dev = dev; ifx_eth_rx(dev,len,skb); return ; rx_err_exit: if (skb) dev_kfree_skb_any(skb); return ; }
int ifxmips_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) { struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)dev->priv; unsigned char *buf = NULL; struct sk_buff *skb = NULL; int len = 0; len = dma_device_read(dma_dev, &buf, (void **)&skb); if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { printk(KERN_INFO "ifxmips_mii0: packet too large %d\n", len); goto ifxmips_mii_hw_receive_err_exit; } /* remove CRC */ len -= 4; if (skb == NULL) { printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n"); goto ifxmips_mii_hw_receive_err_exit; } if (len > (skb->end - skb->tail)) { printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail); goto ifxmips_mii_hw_receive_err_exit; } skb_put(skb, len); skb->dev = dev; skb->protocol = eth_type_trans(skb, dev); netif_rx(skb); priv->stats.rx_packets++; priv->stats.rx_bytes += len; return 0; ifxmips_mii_hw_receive_err_exit: if (len == 0) { if (skb) dev_kfree_skb_any(skb); priv->stats.rx_errors++; priv->stats.rx_dropped++; return -EIO; } else { return len; } }
/*! \fn void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode) * \ingroup IFX_AES_FUNCTIONS * \brief main interface to AES hardware * \param ctx_arg crypto algo context * \param out_arg output bytestream * \param in_arg input bytestream * \param iv_arg initialization vector * \param nbytes length of bytestream * \param encdec 1 for encrypt; 0 for decrypt * \param mode operation mode such as ebc, cbc, ctr * */ void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode) #endif { /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg; u32 *in_key = ctx->buf; unsigned long flag; /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ int key_len = ctx->key_length; #ifndef CONFIG_CRYPTO_DEV_DMA int i = 0; int byte_cnt = nbytes; #else volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; struct dma_device_info *dma_device = ifx_deu[0].dma_device; //deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv; int wlen = 0; u32 *outcopy = NULL; u32 *dword_mem_aligned_in = NULL; #ifdef CONFIG_CRYPTO_DEV_POLL_DMA u32 timeout = 0; u32 *out_dma = NULL; #endif #endif CRTCL_SECT_START; /* 128, 192 or 256 bit key length */ aes->controlr.K = key_len / 8 - 2; if (key_len == 128 / 8) { aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0)); aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1)); aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2)); aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3)); } else if (key_len == 192 / 8) { aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0)); aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1)); aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2)); aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3)); aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4)); aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5)); } else if (key_len == 256 / 8) { aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0)); aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1)); aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2)); aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3)); aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4)); aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5)); aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6)); aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7)); } else { printk (KERN_ERR "[%s %s %d]: Invalid key_len : %d\n", __FILE__, __func__, __LINE__, key_len); CRTCL_SECT_END; return;// -EINVAL; } /* let HW pre-process DEcryption key in any case (even if ENcryption is used). Key Valid (KV) bit is then only checked in decryption routine! */ aes->controlr.PNK = 1; #ifdef CONFIG_CRYPTO_DEV_DMA while (aes->controlr.BUS) { // this will not take long } AES_DMA_MISC_CONFIG(); #endif aes->controlr.E_D = !encdec; //encryption aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps if (mode > 0) { aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg); aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1)); aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2)); aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3)); }; #ifndef CONFIG_CRYPTO_DEV_DMA i = 0; while (byte_cnt >= 16) { aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0)); aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1)); aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2)); aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3)); /* start crypto */ while (aes->controlr.BUS) { // this will not take long } *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R; *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R; *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R; *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R; i++; byte_cnt -= 16; } #else // dma /* memory alignment issue */ dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes); dma->controlr.ALGO = 1; //AES dma->controlr.BS = 0; aes->controlr.DAU = 0; dma->controlr.EN = 1; while (aes->controlr.BUS) { // wait for AES to be ready }; wlen = dma_device_write (dma_device, (u8 *)dword_mem_aligned_in, nbytes, NULL); if (wlen != nbytes) { dma->controlr.EN = 0; CRTCL_SECT_END; printk (KERN_ERR "[%s %s %d]: dma_device_write fail!\n", __FILE__, __func__, __LINE__); return; // -EINVAL; } WAIT_AES_DMA_READY(); outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, aes_buff_out, BUFFER_OUT, nbytes); #ifdef CONFIG_CRYPTO_DEV_POLL_DMA // polling DMA rx channel while ((dma_device_read (dma_device, (u8 **) &out_dma, NULL)) == 0) { timeout++; if (timeout >= 333000) { dma->controlr.EN = 0; CRTCL_SECT_END; printk (KERN_ERR "[%s %s %d]: timeout!!\n", __FILE__, __func__, __LINE__); return; // -EINVAL; } } WAIT_AES_DMA_READY(); AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes); #else /* Prepare Rx buf length used in dma psuedo interrupt */ deu_priv->deu_rx_buf = out_arg; deu_priv->outcopy = outcopy; deu_priv->deu_rx_len = nbytes; CRTCL_SECT_END; /* Sleep and wait for Rx finished */ DEU_WAIT_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags); CRTCL_SECT_START; #endif #endif // dma //tc.chen : copy iv_arg back if (mode > 0) { *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg)); *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1)); *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2)); *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3)); } CRTCL_SECT_END; }