/** * \brief Trigger and wait for a successful transfer * * \param channel_num Channel number */ static void dma_transfer_block(dma_channel_num_t channel_num) { /* Trigger a DMA copy */ dma_channel_trigger_block_transfer(channel_num); /* Wait for it to finish */ while (dma_get_channel_status(channel_num) != DMA_CH_TRANSFER_COMPLETED) { /* Intentionally left empty */ } }
/** * \internal * \brief Common DMA channel interrupt handler * * Calls the channel callback with the channel status code. The following * status codes are possible: * - DMA_CH_TRANSFER_COMPLETED: Transfer completed successfully * - DMA_CH_TRANSFER_ERROR: Fault in transfer * * The optional callback used by the interrupt handler is set by the * dma_set_callback() function. * * \param num DMA channel number to handle interrupt for */ static void dma_interrupt(const dma_channel_num_t num) { enum dma_channel_status status; DMA_CH_t *channel; channel = dma_get_channel_address_from_num(num); status = dma_get_channel_status(num); /* Clear all interrupt flags to be sure */ channel->CTRLB |= DMA_CH_TRNIF_bm | DMA_CH_ERRIF_bm; if (dma_data[num].callback) { dma_data[num].callback(status); } }
/** * \brief Test the error handling of the module * * \note Test error handling by disabling a channel which is in use * * \param test Current test */ static void run_dma_error_handling_test(const struct test_case *test) { /* Enable DMA */ dma_enable(); /* Reset the channel */ dma_channel_reset(DMA_CHANNEL_0); /* Set up channel 0 to do some work, check that is it busy, * change some settings and verify a transfer error */ dma_channel_write_burst_length(DMA_CHANNEL_0, DMA_CH_BURSTLEN_1BYTE_gc); dma_channel_write_transfer_count(DMA_CHANNEL_0, MEMORY_BLOCK_SIZE); dma_channel_write_source(DMA_CHANNEL_0, (uint16_t)(uintptr_t)memory_block_src); dma_channel_write_destination(DMA_CHANNEL_0, (uint16_t)(uintptr_t)memory_block_dest); /* Enable the channel */ dma_channel_enable(DMA_CHANNEL_0); /* Start a block transfer */ dma_channel_trigger_block_transfer(DMA_CHANNEL_0); /* Wait for the channel to become busy */ while (!dma_channel_is_busy(DMA_CHANNEL_0)) { /* Intentionally left empty */ } /* Disable the channel while it is busy */ if (dma_channel_is_busy(DMA_CHANNEL_0)) { dma_channel_disable(DMA_CHANNEL_0); } /* Test whether the channel is in error */ test_assert_true(test, dma_get_channel_status( DMA_CHANNEL_0) == DMA_CH_TRANSFER_ERROR, "DMA channel not in error after disabling during transfer" " write"); dma_disable(); }
/** * \brief Wait for DMA transfer to complete and check status * * \param test Current test case * * \retval true if DMA transfer completed without error * \retval false if DMA transfer failed */ static bool wait_for_dma_transfer(const struct test_case *test) { enum dma_channel_status status; while (1) { status = dma_get_channel_status(CONF_TEST_DMACH); if(status == DMA_CH_TRANSFER_COMPLETED) { return true; } else if(status == DMA_CH_FREE) { test_assert_true(test, false, "DMA channel did not trigger while doing CRC"); return false; } else if(status == DMA_CH_TRANSFER_ERROR) { test_assert_true(test, false, "DMA Transfer error doing CRC"); return false; } } }
/** * * \brief Test double buffering mode * * \note This function tests the double buffering feature of the DMA * controller by configuring channel 0 and 1 to do the same copy, * and verify that the channels enable each other according to * the double buffering process. * * \param test Current test case */ static void run_dma_double_buffering_test(const struct test_case *test) { struct dma_channel_config config_params; bool success = true; /* Assume everything goes well */ /* Fill source block with pattern data */ set_buffer(memory_block_src, 0x00); block_fill(memory_block_src, MEMORY_BLOCK_SIZE); /* Null out the destination block */ set_buffer(memory_block_dest, 0x00); /* Null out the config params */ memset(&config_params, 0, sizeof(config_params)); /* Enable DMA */ dma_enable(); /* Enable double buffering mode on channel 0 and 1 */ dma_set_double_buffer_mode(DMA_DBUFMODE_CH01_gc); /* Set channel 1 to copy from memory_block_src to memory_block_dest */ dma_channel_set_src_reload_mode(&config_params, DMA_CH_SRCRELOAD_NONE_gc); dma_channel_set_src_dir_mode(&config_params, DMA_CH_SRCDIR_INC_gc); dma_channel_set_dest_reload_mode(&config_params, DMA_CH_DESTRELOAD_NONE_gc); dma_channel_set_dest_dir_mode(&config_params, DMA_CH_DESTDIR_INC_gc); dma_channel_set_burst_length(&config_params, DMA_CH_BURSTLEN_1BYTE_gc); dma_channel_set_transfer_count(&config_params, MEMORY_BLOCK_SIZE); dma_channel_set_source_address(&config_params, (uint16_t)(uintptr_t)memory_block_src); dma_channel_set_destination_address(&config_params, (uint16_t)(uintptr_t)memory_block_dest); dma_channel_set_repeats(&config_params, DOUBLE_BUFFER_REPEATS); /* Write config and enable */ dma_channel_write_config(DMA_CHANNEL_0, &config_params); dma_channel_write_config(DMA_CHANNEL_1, &config_params); /* Enable only channel 0 */ dma_channel_enable(DMA_CHANNEL_0); /* Transfer block and wait for it to finish */ dma_channel_trigger_block_transfer(DMA_CHANNEL_0); while (dma_get_channel_status(DMA_CHANNEL_0) != DMA_CH_TRANSFER_COMPLETED) { /* Intentionally left empty */ } /* * If double buffering is working, channel 1 * will be enabled now by the controller */ if (!(dma_channel_is_enabled(DMA_CHANNEL_1))) { success = false; } /* * Disable channel 0, transfer channel 1, * and verify that channel 0 is enabled again by the controller */ dma_channel_disable(DMA_CHANNEL_0); /* Transfer block and wait for it to finish */ dma_channel_trigger_block_transfer(DMA_CHANNEL_1); while (dma_get_channel_status(DMA_CHANNEL_1) != DMA_CH_TRANSFER_COMPLETED) { /* Intentionally left empty */ } /* Verify that channel 0 is enabled again */ if (!(dma_channel_is_enabled(DMA_CHANNEL_0))) { success = false; } test_assert_true(test, success, "Double buffering mode did not function properly"); }