/** USART TX DMA interrupt service routine.
* Should be called from the relevant DMA stream ISR.
* \param s The USART DMA state structure.
*/
void usart_tx_dma_isr(usart_tx_dma_state* s)
{
if (dma_get_interrupt_flag(s->dma, s->stream,
DMA_TEIF | DMA_DMEIF))
/* TODO: Handle error interrupts! */
screaming_death("DMA TX error interrupt");
if (dma_get_interrupt_flag(s->dma, s->stream, DMA_TCIF)) {
/* Interrupt is Transmit Complete. */
/* Clear the DMA transmit complete and half complete interrupt flags. */
dma_clear_interrupt_flags(s->dma, s->stream, DMA_HTIF | DMA_TCIF);
/* Now that the transfer has finished we can increment the read index. */
s->rd = (s->rd + s->xfer_len) % USART_TX_BUFFER_LEN;
if (s->wr != s->rd)
/* Buffer not empty. */
dma_schedule(s);
}
if (dma_get_interrupt_flag(s->dma, s->stream, DMA_FEIF))
/* Clear FIFO error flag */
dma_clear_interrupt_flags(s->dma, s->stream, DMA_HTIF | DMA_FEIF);
}
void dma1_channel1_isr(void) {
//usbd_ep_write_packet(usb_device,0x82,&(x[0]), 4);
//usbd_ep_write_packet(usb_device,0x82, &(adc_samples[0]), 64);
//gpio_port_write(GPIOE, 0xA500);
/*
if (state == 0){
state = 20;
TIM3_SMCR |= TIM_SMCR_SMS_TM;
}
*/
if ( dma_get_interrupt_flag(DMA1, 1, DMA_TCIF) != 0 ) {
state = 0;
gpio_port_write(GPIOE, 0xA500);
dma_clear_interrupt_flags(DMA1, 1, DMA_TCIF);
//gpio_port_write(GPIOE, 0xFF00);
//usbd_ep_write_packet(usb_device,0x82,&(x[0]), 4);
//((uint32_t *) adc_samples)[0] = ADC1_CR;
//((uint32_t *) adc_samples)[1] = ADC1_ISR;
//((uint32_t *) adc_samples)[2] = DMA1_CCR1;
usbd_ep_write_packet(usb_device,0x82, (uint8_t *) &(adc_samples[0]), 62);
// ((uint32_t *) x)[0] = DMA1_CCR1;
//usbd_ep_write_packet(usb_device,0x82, x, 4);
// reset DMA so we're ready to transmit again
}
}
void dma1_stream5_isr(void)
{
if (dma_get_interrupt_flag(DMA1, DMA_STREAM5, DMA_TCIF)) {
dma_clear_interrupt_flags(DMA1, DMA_STREAM5, DMA_TCIF);
/* Toggle PC1 just to keep aware of activity and frequency. */
gpio_toggle(GPIOC, GPIO1);
}
}
/*--------------------------------------------------------------------*/
void dma2_stream0_isr(void)
{
if (dma_get_interrupt_flag(DMA2, DMA_STREAM0, DMA_TCIF))
{
dma_clear_interrupt_flags(DMA2, DMA_STREAM0, DMA_TCIF);
}
if (++cntr > 63)
{
cntr=0;
}
}
void dma2_stream0_isr(void) {
if (dma_get_interrupt_flag(DMA2, DMA_STREAM0, DMA_TCIF)) {
dma_clear_interrupt_flags(DMA2, DMA_STREAM0, DMA_TCIF);
for (int i = 0; i < NUM_SENSORS; ++i) {
if (config.sensors[i].method == SENSOR_ADC) {
config.sensors[i].raw_value = (uint32_t)adc_dma_buf[i];
}
}
sensor_adc_new_data();
}
}
/** DMA 2 Stream 3 Interrupt Service Routine. (SPI1_TX) */
void dma2_stream3_isr(void)
{
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
if (dma_get_interrupt_flag(DMA2, 3, DMA_TEIF | DMA_DMEIF))
screaming_death("DMA SPI1_TX error interrupt");
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
/** USART RX DMA interrupt service routine.
* Should be called from the relevant DMA stream ISR.
* \param s The USART DMA state structure.
*/
void usart_rx_dma_isr(usart_rx_dma_state* s)
{
if (dma_get_interrupt_flag(s->dma, s->stream,
DMA_TEIF | DMA_DMEIF | DMA_FEIF))
/* TODO: Handle error interrupts! */
screaming_death("USART RX DMA error interrupt");
if (dma_get_interrupt_flag(s->dma, s->stream, DMA_HTIF | DMA_TCIF)) {
/* Interrupt is Transmit Complete. We are in circular buffer mode so this
* probably means we just wrapped the buffer. */
/* Clear the DMA transmit complete and half complete interrupt flags. */
dma_clear_interrupt_flags(s->dma, s->stream, DMA_HTIF | DMA_TCIF);
/* Increment our write wrap counter. */
s->wr_wraps++;
}
/* Note: When DMA is re-enabled after bootloader it appears ISR can get
* called without any of the bits of DMA_LISR being high */
}
void dma1_channel1_isr(void)
{
/* Half dma transfer interrupt. */
if (dma_get_interrupt_flag(DMA1, DMA_CHANNEL1, DMA_HTIF)) {
if (adc_state.half_transfer_callback) {
adc_state.half_transfer_callback(false,
adc_state.raw_data);
}
}
if (dma_get_interrupt_flag(DMA1, DMA_CHANNEL1, DMA_TCIF)) {
if (adc_state.transfer_complete_callback) {
adc_state.transfer_complete_callback(true,
adc_state.raw_data);
}
}
if (dma_get_interrupt_flag(DMA1, DMA_CHANNEL1, DMA_TEIF)) {
adc_state.dma_transfer_error_counter++;
}
dma_clear_interrupt_flags(DMA1, DMA_CHANNEL1, DMA_FLAGS);
}
void dma1_channel1_isr(void) {
//usbd_ep_write_packet(usb_device,0x82,&(x[0]), 4);
//usbd_ep_write_packet(usb_device,0x82, &(adc_samples[0]), 64);
//gpio_port_write(GPIOE, 0xA500);
if ( dma_get_interrupt_flag(DMA1, 1, DMA_TCIF) != 0 ) {
dma_clear_interrupt_flags(DMA1, 1, DMA_TCIF);
gpio_port_write(GPIOE, 0xFF00);
//usbd_ep_write_packet(usb_device,0x82,&(x[0]), 4);
usbd_ep_write_packet(usb_device,0x82, (uint8_t *) &(adc_samples[0]), 62);
// ((uint32_t *) x)[0] = DMA1_CCR1;
//usbd_ep_write_packet(usb_device,0x82, x, 4);
// reset DMA so we're ready to transmit again
}
}
/** DMA 2 Stream 0 Interrupt Service Routine. (SPI1_RX) */
void dma2_stream0_isr(void)
{
CH_IRQ_PROLOGUE();
chSysLockFromIsr();
if (dma_get_interrupt_flag(DMA2, 0, DMA_TEIF | DMA_DMEIF))
screaming_death("DMA SPI1_RX error interrupt");
/* Disable both receive and transmit streams */
dma_clear_interrupt_flags(DMA2, 3, DMA_TCIF | DMA_HTIF);
dma_clear_interrupt_flags(DMA2, 0, DMA_TCIF | DMA_HTIF);
/* Signal the semaphore to wake up blocking spi1_xfer_dma */
chBSemSignalI(&spi_dma_sem);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
/** Write out data over the USART using DMA.
* Note that this function is not reentrant and does not guard against DMA IRQs
* running at the same time which will also cause spurious behaviours. Ensure
* that the calling function prevents this from happening.
*
* \param s The USART DMA state structure.
* \param data A pointer to the data to write out.
* \param len The number of bytes to write.
* \return The number of bytes that will be written, may be less than len.
*/
u32 usart_write_dma(usart_tx_dma_state* s, u8 data[], u32 len)
{
/* If there is no data to write, just return. */
if (len == 0) return 0;
/* Check if the write would cause a buffer overflow, if so only write up to
* the end of the buffer. */
u32 n_free = usart_tx_n_free(s);
if (len > n_free)
return 0;
u32 old_wr = s->wr;
s->wr = (s->wr + len) % USART_TX_BUFFER_LEN;
if (old_wr + len <= USART_TX_BUFFER_LEN)
memcpy(&(s->buff[old_wr]), data, len);
else {
/* Deal with case where write wraps the buffer. */
memcpy(&(s->buff[old_wr]), &data[0], USART_TX_BUFFER_LEN - old_wr);
memcpy(&(s->buff[0]), &data[USART_TX_BUFFER_LEN - old_wr],
len - (USART_TX_BUFFER_LEN - old_wr));
}
/* Check if there is a DMA transfer either in progress or waiting for its
* interrupt to be serviced. Its very important to also check the interrupt
* flag as EN will be cleared when the transfer finishes but we really need
* to make sure the ISR has been run to finish up the bookkeeping for the
* transfer. Also, make sure that this is done atomically without a DMA
* interrupt squeezing in there. */
if (!((DMA_SCR(s->dma, s->stream) & DMA_SxCR_EN) ||
dma_get_interrupt_flag(s->dma, s->stream, DMA_TCIF)))
dma_schedule(s);
s->byte_counter += len;
return len;
}
void dma1_channel1_isr(void) {
if (dma_get_interrupt_flag(DMA1, DMA_CHANNEL1, DMA_TCIF)) {
dma_clear_interrupt_flags(DMA1, DMA_CHANNEL1, DMA_TCIF);
sampler_dma_completed_handler(&sampler);
}
}
