void ddr_enable_ecc(unsigned int dram_size) { volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* * Enable errors for ECC. */ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); ddr->err_disable = 0x00000000; asm("sync;isync;msync"); debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); }
void ddr_enable_ecc(unsigned int dram_size) { struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* * Enable errors for ECC. */ debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); ddr->err_disable = 0x00000000; asm("sync;isync;msync"); debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); }
phys_size_t initdram (int board_type) { long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ temp_ddrdll = gur->ddrdllcr; gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; asm("sync;isync;msync"); #endif #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else dram_size = fixed_sdram (); #endif #if defined(CONFIG_SYS_RAMBOOT) return dram_size; #endif #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ lbc->br2 = CONFIG_SYS_BR2_PRELIM; lbc->lbcr = CONFIG_SYS_LBC_LBCR; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); * (ulong *)0 = 0x000000ff; lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif #if defined(CONFIG_DDR_ECC) { /* Initialize all of memory for ECC, then * enable errors */ volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); /* Enable errors for ECC */ ddr->err_disable = 0x00000000; asm("sync;isync;msync"); } #endif return dram_size; }