int dmacHw_initChannel(dmacHw_HANDLE_t handle
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
int module = pCblk->module;
int channel = pCblk->channel;
memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
pCblk->module = module;
pCblk->channel = channel;
dmacHw_DMA_ENABLE(pCblk->module);
dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
return 0;
}
int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
int module = pCblk->module;
int channel = pCblk->channel;
/* Reinitialize the control block */
memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
pCblk->module = module;
pCblk->channel = channel;
/* Enable DMA controller */
dmacHw_DMA_ENABLE(pCblk->module);
/* Reset DMA channel */
dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
/* Clear all raw interrupt status */
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
/* Mask event specific interrupts */
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
return 0;
}
int dmacHw_configChannel(dmacHw_HANDLE_t handle,
dmacHw_CONFIG_t *pConfig
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
uint32_t cfgHigh = 0;
int srcTrSize;
int dstTrSize;
pCblk->varDataStarted = 0;
pCblk->userData = NULL;
cfgHigh =
dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
dmacHw_SRC_PERI_INTF(pConfig->
srcPeripheralPort) |
dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
pConfig->channelPriority);
if (pConfig->dstStatusRegisterAddress != 0) {
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
pConfig->dstStatusRegisterAddress);
}
if (pConfig->srcStatusRegisterAddress != 0) {
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
pConfig->srcStatusRegisterAddress);
}
dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
}
if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
}
if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
}
if (pConfig->srcGatherWidth) {
srcTrSize =
dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
if (!
((pConfig->srcGatherWidth % srcTrSize)
&& (pConfig->srcGatherJump % srcTrSize))) {
dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
((pConfig->srcGatherWidth /
srcTrSize) << 20) | (pConfig->srcGatherJump /
srcTrSize);
} else {
return -1;
}
}
if (pConfig->dstScatterWidth) {
dstTrSize =
dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
if (!
((pConfig->dstScatterWidth % dstTrSize)
&& (pConfig->dstScatterJump % dstTrSize))) {
dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
((pConfig->dstScatterWidth /
dstTrSize) << 20) | (pConfig->dstScatterJump /
dstTrSize);
} else {
return -1;
}
}
return 0;
}
int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
uint32_t cfgHigh = 0;
int srcTrSize;
int dstTrSize;
pCblk->varDataStarted = 0;
pCblk->userData = NULL;
/* Configure
- Burst transaction when enough data in available in FIFO
- AHB Access protection 1
- Source and destination peripheral ports
*/
cfgHigh =
dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
dmacHw_SRC_PERI_INTF(pConfig->
srcPeripheralPort) |
dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
/* Set priority */
dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
pConfig->channelPriority);
if (pConfig->dstStatusRegisterAddress != 0) {
/* Destination status update enable */
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
/* Configure status registers */
dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
pConfig->dstStatusRegisterAddress);
}
if (pConfig->srcStatusRegisterAddress != 0) {
/* Source status update enable */
cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
/* Source status update enable */
dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
pConfig->srcStatusRegisterAddress);
}
/* Configure the config high register */
dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
/* Clear all raw interrupt status */
dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
/* Configure block interrupt */
if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure complete transfer interrupt */
if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure error interrupt */
if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
} else {
dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
}
/* Configure gather register */
if (pConfig->srcGatherWidth) {
srcTrSize =
dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
if (!
((pConfig->srcGatherWidth % srcTrSize)
&& (pConfig->srcGatherJump % srcTrSize))) {
dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
((pConfig->srcGatherWidth /
srcTrSize) << 20) | (pConfig->srcGatherJump /
srcTrSize);
} else {
return -1;
}
}
/* Configure scatter register */
if (pConfig->dstScatterWidth) {
dstTrSize =
dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
if (!
((pConfig->dstScatterWidth % dstTrSize)
&& (pConfig->dstScatterJump % dstTrSize))) {
dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
((pConfig->dstScatterWidth /
dstTrSize) << 20) | (pConfig->dstScatterJump /
dstTrSize);
} else {
return -1;
}
}
return 0;
}
