static irqreturn_t
hr_time_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
ixp2000_reg_write(IXP2000_T2_CTL, 0);
ixp2000_reg_write(IXP2000_T2_CLR, 1);
do_hr_timer_int();
return IRQ_HANDLED;
}
static void
hr_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
volatile mputimer_regs_t * subhz_timer = mputimer_base(2);
subhz_timer->cntl = 0;
#ifdef CONFIG_VST
update_jiffies_vst();
#endif
do_hr_timer_int();
}
/*
* HR interrupt.
*/
static irqreturn_t
hr_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
volatile TimerStruct_t *subhz_timer =
(volatile TimerStruct_t *) TIMER2_VA_BASE;
subhz_timer->TimerClear = 1;
subhz_timer->TimerControl = 0;
do_hr_timer_int();
return IRQ_HANDLED;
}
inline void smp_local_timer_interrupt(struct pt_regs * regs)
{
int cpu = smp_processor_id();
#ifdef CONFIG_HIGH_RES_TIMERS
if (! per_cpu(prof_counter, cpu))
do_hr_timer_int();
#endif
profile_tick(CPU_PROFILING, regs);
if (--per_cpu(prof_counter, cpu) <= 0) {
/*
* The multiplier may have changed since the last time we got
* to this point as a result of the user writing to
* /proc/profile. In this case we need to adjust the APIC
* timer accordingly.
*
* Interrupts are already masked off at this point.
*/
per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
if (per_cpu(prof_counter, cpu) !=
per_cpu(prof_old_multiplier, cpu)) {
__setup_APIC_LVTT(
calibration_result/
per_cpu(prof_counter, cpu));
per_cpu(prof_old_multiplier, cpu) =
per_cpu(prof_counter, cpu);
#ifdef CONFIG_HIGH_RES_TIMERS
return;
#endif
}
#ifdef CONFIG_HIGH_RES_TIMERS
apic_write_around(APIC_TMICT, calibration_result /
per_cpu(prof_counter, cpu));
#else
#ifdef CONFIG_SMP
update_process_times(user_mode(regs));
#endif
#endif
}
/*
* We take the 'long' return path, and there every subsystem
* grabs the apropriate locks (kernel lock/ irq lock).
*
* we might want to decouple profiling from the 'long path',
* and do the profiling totally in assembly.
*
* Currently this isn't too much of an issue (performance wise),
* we can take more than 100K local irqs per second on a 100 MHz P5.
*/
}
/*!
* IRQ handler for the timer
*/
static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
#ifdef CONFIG_HIGH_RES_TIMERS
if (__raw_readl(HSTIM_INT) & MATCH1_INT) {
__raw_writel(__raw_readl(HSTIM_MCTRL) & ~MR1_INT, HSTIM_MCTRL);
__raw_writel(MATCH1_INT, HSTIM_INT);
do_hr_timer_int();
}
#endif /* CONFIG_HIGH_RES_TIMERS */
#ifdef CONFIG_FRD
if (__raw_readl(HSTIM_INT) & MATCH1_INT)
return IRQ_NONE;
#endif
if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
write_seqlock(&xtime_lock);
do {
timer_tick(regs);
/*
* this algorithm takes care of possible delay
* for this interrupt handling longer than a normal
* timer period
*/
__raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
HSTIM_MATCH0);
__raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
/*
* The goal is to keep incrementing HSTIM_MATCH0
* register until HSTIM_MATCH0 indicates time after
* what HSTIM_COUNTER indicates.
*/
} while ((signed)
(__raw_readl(HSTIM_MATCH0) -
__raw_readl(HSTIM_COUNTER)) < 0);
write_sequnlock(&xtime_lock);
}
return IRQ_HANDLED;
}
/*!
* This is the timer interrupt service routine to do required tasks.
* It also services the WDOG timer at the frequency of twice per WDOG
* timeout value. For example, if the WDOG's timeout value is 4 (2
* seconds since the WDOG runs at 0.5Hz), it will be serviced once
* every 2/2=1 second.
*
* @param irq GPT interrupt source number (not used)
* @param dev_id this parameter is not used
* @param regs pointer to a structure containing the processor
* registers and state prior to servicing the interrupt
* @return always returns \b IRQ_HANDLED as defined in
* include/linux/interrupt.h.
*/
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
unsigned int next_match;
#ifdef CONFIG_HIGH_RES_TIMERS
u32 reg;
if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF2) {
__raw_writel(GPTSR_OF2, MXC_GPT_GPTSR);
reg = __raw_readl(MXC_GPT_GPTIR);
reg &= ~GPTIR_OF2IE;
reg = __raw_writel(reg, MXC_GPT_GPTIR);
do_hr_timer_int();
}
#endif
write_seqlock(&xtime_lock);
if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1)
do {
#ifdef WDOG_SERVICE_PERIOD
if ((g_wdog1_enabled || g_wdog2_enabled) &&
(++g_wdog_count >=
((WDOG_SERVICE_PERIOD / 1000) * HZ))) {
kick_wd();
g_wdog_count = 0; /* reset */
}
#else
kick_wd();
#endif /* WDOG_SERVICE_PERIOD */
timer_tick(regs);
next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
__raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
__raw_writel(next_match, MXC_GPT_GPTOCR1);
} while ((signed long)(next_match -
__raw_readl(MXC_GPT_GPTCNT)) <= 0);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
