Example #1
0
static void intel_dsi_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 temp;

	DRM_DEBUG_KMS("\n");

	if (is_cmd_mode(intel_dsi))
		I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
	else {
		msleep(20); /* XXX */
		dpi_send_cmd(intel_dsi, TURN_ON);
		msleep(100);

		/* assert ip_tg_enable signal */
		temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
		temp = temp | intel_dsi->port_bits;
		I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
		POSTING_READ(MIPI_PORT_CTRL(pipe));
	}

	if (intel_dsi->dev.dev_ops->enable)
		intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
}
Example #2
0
static void intel_dsi_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 temp;

	DRM_DEBUG_KMS("\n");

	if (is_vid_mode(intel_dsi)) {
		dpi_send_cmd(intel_dsi, SHUTDOWN);
		msleep(10);

		/* de-assert ip_tg_enable signal */
		temp = I915_READ(MIPI_PORT_CTRL(pipe));
		I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
		POSTING_READ(MIPI_PORT_CTRL(pipe));

		msleep(2);
	}

	/* if disable packets are sent before sending shutdown packet then in
	 * some next enable sequence send turn on packet error is observed */
	if (intel_dsi->dev.dev_ops->disable)
		intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
}
static void intel_dsi_disable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 temp;

	DRM_DEBUG_KMS("\n");

	intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);

	if (is_vid_mode(intel_dsi)) {
		dpi_send_cmd(intel_dsi, SHUTDOWN);
		msleep(10);

		/* de-assert ip_tg_enable signal */
		temp = I915_READ(MIPI_PORT_CTRL(pipe));
		I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
		POSTING_READ(MIPI_PORT_CTRL(pipe));

		msleep(2);
	}

	temp = I915_READ(MIPI_DEVICE_READY(pipe));
	if (temp & DEVICE_READY) {
		temp &= ~DEVICE_READY;
		temp &= ~ULPS_STATE_MASK;
		I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
	}
}
static void intel_dsi_disable(struct intel_encoder *encoder)
{
#ifndef BYT_DUAL_MIPI_DSI
	struct drm_encoder *drm_encoder = &encoder->base;
	struct drm_device *dev = encoder->base.dev;
#endif
	//struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	//struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	DRM_DEBUG_KMS("\n");

//XXX dual display use mipi backlight for debug only
#ifndef BYT_DUAL_MIPI_DSI
	intel_panel_disable_backlight(dev);
#endif
	if (intel_dsi->backlight_off_delay >= 20)
		msleep(intel_dsi->backlight_off_delay);
	else
		usleep_range(intel_dsi->backlight_off_delay * 1000,
			(intel_dsi->backlight_off_delay * 1000) + 500);

	if (is_cmd_mode(intel_dsi)) {
		/* XXX Impementation TBD */
	} else {
		/* Send Shutdown command to the panel in LP mode */
		intel_dsi->hs = 1;
		dpi_send_cmd(intel_dsi, SHUTDOWN);
		usleep_range(1000, 1500);
	}
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	DRM_DEBUG_KMS("\n");

	intel_enable_dsi_pll(intel_dsi);

	if (is_cmd_mode(intel_dsi)) {
		/* XXX: Implement me */
		I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
	}
	else {
		intel_dsi->hs = 0;
		dpi_send_cmd(intel_dsi, TURN_ON);
		usleep_range(1000, 1500);
		if (intel_dsi->dev.dev_ops->enable)
			intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);

		intel_dsi_port_enable(encoder);
	}
}
Example #6
0
static void intel_dsi_pre_disable(struct intel_encoder *encoder)
{
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	DRM_DEBUG_KMS("\n");

	if (is_vid_mode(intel_dsi)) {
		/* Send Shutdown command to the panel in LP mode */
		dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN);
		msleep(10);
	}
}
static void intel_dsi_enable(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	u32 temp;

	DRM_DEBUG_KMS("\n");

	temp = I915_READ(MIPI_DEVICE_READY(pipe));
	if ((temp & DEVICE_READY) == 0) {
		temp &= ~ULPS_STATE_MASK;
		I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
	} else if (temp & ULPS_STATE_MASK) {
		temp &= ~ULPS_STATE_MASK;
		I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
		/*
		 * We need to ensure that there is a minimum of 1 ms time
		 * available before clearing the UPLS exit state.
		 */
		msleep(2);
		I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
	}

	if (is_cmd_mode(intel_dsi))
		I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);

	if (is_vid_mode(intel_dsi)) {
		msleep(20); /* XXX */
		dpi_send_cmd(intel_dsi, TURN_ON);
		msleep(100);

		/* assert ip_tg_enable signal */
		temp = I915_READ(MIPI_PORT_CTRL(pipe));
		I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
		POSTING_READ(MIPI_PORT_CTRL(pipe));
	}

	intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
}
static void intel_dsi_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
	int pipe = intel_crtc->pipe;
	bool is_dsi;
	u32 temp;
	DRM_DEBUG_KMS("\n");

	is_dsi = intel_pipe_has_type(encoder->base.crtc, INTEL_OUTPUT_DSI);
	intel_enable_dsi_pll(intel_dsi);

	printk("====>DLP3430 debug 2.20.\n");

	if (is_cmd_mode(intel_dsi)) {
		/* XXX: Implement me */
		I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
	}
	else {
		intel_dsi->hs = 1;
		dpi_send_cmd(intel_dsi, TURN_ON);
		usleep_range(1000, 1500);

		if (intel_dsi->dev.dev_ops->enable)
			intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);

		temp = I915_READ(MIPI_PORT_CTRL(pipe));
		temp = temp | intel_dsi->port_bits;

		if (is_dsi && intel_crtc->config.dither)
			temp |= DITHERING_ENABLE;
		I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
		usleep_range(2000, 2500);
	}
}
static void intel_dsi_disable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	DRM_DEBUG_KMS("\n");

	intel_panel_disable_backlight(dev);
	if (intel_dsi->backlight_off_delay >= 20)
		msleep(intel_dsi->backlight_off_delay);
	else
		usleep_range(intel_dsi->backlight_off_delay * 1000,
			(intel_dsi->backlight_off_delay * 1000) + 500);

	if (is_cmd_mode(intel_dsi)) {
		/* XXX Impementation TBD */
	} else {
		/* Send Shutdown command to the panel in LP mode */
		intel_dsi->hs = 0;
		dpi_send_cmd(intel_dsi, SHUTDOWN);
		usleep_range(1000, 1500);

	}
}