void dphy_init(u32 bps_per_lane, u32 phy_id) { #if IS_ENABLED(VERSION3L) || IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D) dpy_ab_clr(); if (phy_id & 0x01) { dpy_a_enable(); dphy_init_common(bps_per_lane, phy_id, 0); } if (phy_id & 0x02) { dpy_b_enable(); dphy_init_common(bps_per_lane, phy_id, 1); } if (0x03 == (phy_id & 0x03)) { dpy_ab_sync(); } if (phy_id & 0x04) { dpy_c_enable(); dphy_init_common(bps_per_lane, phy_id, 0); } #else dphy_init_common(bps_per_lane, phy_id, 0); #endif }
void dphy_init(u32 pclk, u32 phy_id) { #if defined(CONFIG_ARCH_SCX30G) dpy_ab_clr(); if (phy_id & 0x01) { dpy_a_enable(); dphy_init_common(pclk, phy_id, 0); } if (phy_id & 0x02) { dpy_b_enable(); dphy_init_common(pclk, phy_id, 1); } if (0x03 == (phy_id & 0x03)) { dpy_ab_sync(); } #else dphy_init_common(pclk, phy_id, 1); #endif }