struct drm_display_mode *b080xat_get_modes(struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 768;
mode->hsync_start = 828;
mode->hsync_end = 892;
mode->htotal = 948;
mode->vdisplay = 1024;
mode->vsync_start = 1160;
mode->vsync_end = 1210;
mode->vtotal = 1240;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static
struct drm_display_mode *sdc16x25_8_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = WIDTH;
mode->hsync_start = mode->hdisplay + 48;
mode->hsync_end = mode->hsync_start + 32;
mode->htotal = mode->hsync_end + 80;
mode->vdisplay = HEIGHT;
mode->vsync_start = mode->vdisplay + 3;
mode->vsync_end = mode->vsync_start + 33;
mode->vtotal = mode->vsync_end + 10;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static
bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
struct drm_display_mode *fixed_mode;
if (!dsi_config) {
DRM_ERROR("dsi_config is NULL\n");
return;
}
fixed_mode = dsi_config->fixed_mode;
PSB_DEBUG_ENTRY("\n");
if (fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
return true;
}
static struct drm_display_mode *kd080d10_31na_a11_get_modes(
struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode = NULL;
struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
/* Allocate */
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) {
DRM_DEBUG_KMS("Cpt panel: No memory\n");
return NULL;
}
mode->hdisplay = 800;
mode->hsync_start = mode->hdisplay + 24; /*mode->hdisplay + HFP;*/
mode->hsync_end = mode->hsync_start + 4; /*mode->hsync_start + HSYNC;*/
mode->htotal = mode->hsync_end + 132; /*mode->hsync_end + HBP;*/
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 8; /*mode->vdisplay + VFP;*/
mode->vsync_end = mode->vsync_start + 4; /*mode->vsync_start + VSYNC;*/
mode->vtotal = mode->vsync_end + 8; /*mode->vsync_end + VBP;*/
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
intel_dsi->pclk = mode->clock;
/* Configure */
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static struct drm_display_mode *p088pw_get_modes(
struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode = NULL;
DRM_DEBUG_KMS("\n");
/* Allocate */
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) {
DRM_DEBUG_KMS("Cpt panel: No memory\n");
return NULL;
}
mode->hdisplay = 1920;
mode->vdisplay = 1200;
mode->hsync_start = mode->hdisplay + 20; //HFP
mode->hsync_end = mode->hsync_start + 16; //HSW
mode->htotal = mode->hsync_end + 15; //HBP
mode->vsync_start = mode->vdisplay + 15; //VFP
mode->vsync_end = mode->vsync_start + 2;//VSW
mode->vtotal = mode->vsync_end + 3;//VBP
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *mode->htotal / 1000;//VCLK
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
struct drm_display_mode *otm1901a_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
printk("[DISP] %s\n", __func__);
/* RECOMMENDED PORCH SETTING
HSA=4, HBP=50, HFP=50
VSA=1, VBP=9, VFP=14 */
mode->hdisplay = 1080;
mode->hsync_start = mode->hdisplay + 50;
mode->hsync_end = mode->hsync_start + 4;
mode->htotal = mode->hsync_end + 50;
mode->vdisplay = 1920;
mode->vsync_start = mode->vdisplay + 16;
mode->vsync_end = mode->vsync_start + 1;
mode->vtotal = mode->vsync_end + 15;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static struct drm_display_mode *n080ice_gb1_get_modes(
struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode = NULL;
DRM_DEBUG_KMS("\n");
/* Allocate */
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) {
DRM_DEBUG_KMS("Cpt panel: No memory\n");
return NULL;
}
mode->hdisplay = 800;
mode->hsync_start = mode->hdisplay + 16;
mode->hsync_end = mode->hsync_start + 48;
mode->htotal = mode->hsync_end + 16;
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 4;
mode->vsync_end = mode->vsync_start + 8;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
/* Configure */
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static struct drm_display_mode *sharp5_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 1080;
mode->hsync_start = 1168;
mode->hsync_end = 1200;
mode->htotal = 1496;
mode->vdisplay = 1920;
mode->vsync_start = 1923;
mode->vsync_end = 1926;
mode->vtotal = 1987;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static
bool mdfld_generic_dsi_dbi_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_dbi_output *dbi_output =
MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
struct drm_display_mode *fixed_mode = dbi_output->panel_fixed_mode;
PSB_DEBUG_ENTRY("\n");
if (fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
return true;
}
static bool pyr_dsi_dbi_mode_fixup(struct drm_encoder * encoder,
struct drm_display_mode * mode,
struct drm_display_mode * adjusted_mode)
{
struct drm_device* dev = encoder->dev;
struct drm_display_mode * fixed_mode = pyr_cmd_get_config_mode(dev);
PSB_DEBUG_ENTRY("\n");
if(fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
kfree(fixed_mode);
}
return true;
}
static struct drm_display_mode *hannstar_get_modes(
struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode = NULL;
DRM_DEBUG("[DISPLAY] %s: Enter\n", __func__);
/* Allocate */
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) {
DRM_DEBUG_KMS("Panasonic panel: No memory\n");
return NULL;
}
/* Hardcode 1920x1200 */
mode->hdisplay = 1920;
mode->hsync_start = mode->hdisplay + 16;
mode->hsync_end = mode->hsync_start + 32;
mode->htotal = mode->hsync_end + 16;
mode->vdisplay = 1200;
mode->vsync_start = mode->vdisplay + 2;
mode->vsync_end = mode->vsync_start + 18;
mode->vtotal = mode->vsync_end + 15;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
/* Configure */
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
if (!BYT_CR_CONFIG)
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static struct drm_display_mode *tpo_vid_get_config_mode(struct drm_device *dev)
{
struct drm_display_mode *mode;
struct drm_psb_private *dev_priv = dev->dev_private;
struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
bool use_gct = false;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
if (use_gct) {
mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
mode->hsync_start = mode->hdisplay +
((ti->hsync_offset_hi << 8) |
ti->hsync_offset_lo);
mode->hsync_end = mode->hsync_start +
((ti->hsync_pulse_width_hi << 8) |
ti->hsync_pulse_width_lo);
mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) |
ti->hblank_lo);
mode->vsync_start =
mode->vdisplay + ((ti->vsync_offset_hi << 8) |
ti->vsync_offset_lo);
mode->vsync_end =
mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) |
ti->vsync_pulse_width_lo);
mode->vtotal = mode->vdisplay +
((ti->vblank_hi << 8) | ti->vblank_lo);
mode->clock = ti->pixel_clock * 10;
dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay);
dev_dbg(dev->dev, "vdisplay is %d\n", mode->vdisplay);
dev_dbg(dev->dev, "HSS is %d\n", mode->hsync_start);
dev_dbg(dev->dev, "HSE is %d\n", mode->hsync_end);
dev_dbg(dev->dev, "htotal is %d\n", mode->htotal);
dev_dbg(dev->dev, "VSS is %d\n", mode->vsync_start);
dev_dbg(dev->dev, "VSE is %d\n", mode->vsync_end);
dev_dbg(dev->dev, "vtotal is %d\n", mode->vtotal);
dev_dbg(dev->dev, "clock is %d\n", mode->clock);
} else {
mode->hdisplay = 864;
mode->vdisplay = 480;
mode->hsync_start = 873;
mode->hsync_end = 876;
mode->htotal = 887;
mode->vsync_start = 487;
mode->vsync_end = 490;
mode->vtotal = 499;
mode->clock = 33264;
}
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static struct drm_display_mode *jdi_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 720;
mode->hsync_start = 816;
mode->hsync_end = 818;
mode->htotal = 920;
mode->vdisplay = 1280;
mode->vsync_start = 1288;
mode->vsync_end = 1296;
mode->vtotal = 1304;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static
struct drm_display_mode *jdi25x16_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 2560;
mode->hsync_start = mode->hdisplay + 160;
mode->hsync_end = mode->hsync_start + 24;
mode->htotal = mode->hsync_end + 56;
mode->vdisplay = 1600;
mode->vsync_start = mode->vdisplay + 12;
mode->vsync_end = mode->vsync_start + 4;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
struct drm_display_mode *pr2_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 800;
mode->vdisplay = 1024;
mode->hsync_start = 823;
mode->hsync_end = 831;
mode->htotal = 847;
mode->vsync_start = 1031;
mode->vsync_end = 1033;
mode->vtotal = 1035;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static struct drm_display_mode *smd_qhd_amoled_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 540;
mode->vdisplay = 960;
/* HFP = 90, HSYNC = 10, HBP = 20 */
mode->hsync_start = mode->hdisplay + 90;
mode->hsync_end = mode->hsync_start + 10;
mode->htotal = mode->hsync_end + 20;
/* VFP = 4, VSYNC = 2, VBP = 4 */
mode->vsync_start = mode->vdisplay + 4;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * (mode->vtotal + 1) *
(mode->htotal + 1) / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
struct drm_display_mode *samsungWQHD_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
printk("[DISP] %s\n", __func__);
/* RECOMMENDED PORCH SETTING
HSA=, HBP=, HFP=
VSA=, VBP=, VFP= */
mode->hdisplay = 1440;
mode->hsync_start = mode->hdisplay + 48;
mode->hsync_end = mode->hsync_start + 32;
mode->htotal = mode->hsync_end + 80;
mode->vdisplay = 2560;
mode->vsync_start = mode->vdisplay + 3;
mode->vsync_end = mode->vsync_start + 33;
mode->vtotal = mode->vsync_end + 10;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
struct drm_display_mode *lpm070w425b_get_modes(struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
/* beta = 00, alpha = 45 */
/* from renesas spec alpha + beta <= 45 */
mode->hdisplay = 1200;
mode->hsync_start = 1300;
mode->hsync_end = 1340;
mode->htotal = 1380;
/* Added more vblank so more time for frame update */
mode->vdisplay = 1920;
mode->vsync_start = 1925;
mode->vsync_end = 1930;
mode->vtotal = 1935;
mode->vrefresh = 60;
mode->clock = (mode->vrefresh * mode->vtotal *
mode->htotal) / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
void
intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
{
drm_mode_copy(adjusted_mode, fixed_mode);
drm_mode_set_crtcinfo(adjusted_mode, 0);
}
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
{
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
struct drm_display_mode*
pyr_cmd_get_config_mode(struct drm_device* dev)
{
struct drm_display_mode *mode;
/*struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;*/
/*struct mrst_timing_info *ti = &dev_priv->gct_data.DTD;*/
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
PSB_DEBUG_ENTRY("hdisplay is %d\n", mode->hdisplay);
PSB_DEBUG_ENTRY("vdisplay is %d\n", mode->vdisplay);
PSB_DEBUG_ENTRY("HSS is %d\n", mode->hsync_start);
PSB_DEBUG_ENTRY("HSE is %d\n", mode->hsync_end);
PSB_DEBUG_ENTRY("htotal is %d\n", mode->htotal);
PSB_DEBUG_ENTRY("VSS is %d\n", mode->vsync_start);
PSB_DEBUG_ENTRY("VSE is %d\n", mode->vsync_end);
PSB_DEBUG_ENTRY("vtotal is %d\n", mode->vtotal);
PSB_DEBUG_ENTRY("clock is %d\n", mode->clock);
mode->hdisplay = 480;
mode->vdisplay = 864;
mode->hsync_start = 487;
mode->hsync_end = 490;
mode->htotal = 499;
mode->vsync_start = 874;
mode->vsync_end = 878;
mode->vtotal = 886;
mode->clock = 25777;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static
struct drm_display_mode *auo_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 540;
mode->vdisplay = 960;
/* HFP = 40, HSYNC = 10, HBP = 20 */
mode->hsync_start = mode->hdisplay + 40;
mode->hsync_end = mode->hsync_start + 10;
mode->htotal = mode->hsync_end + 20;
/* VFP = 4, VSYNC = 2, VBP = 4 */
mode->vsync_start = mode->vdisplay + 4;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
PSB_DEBUG_ENTRY("hdisplay is %d\n", mode->hdisplay);
PSB_DEBUG_ENTRY("vdisplay is %d\n", mode->vdisplay);
PSB_DEBUG_ENTRY("HSS is %d\n", mode->hsync_start);
PSB_DEBUG_ENTRY("HSE is %d\n", mode->hsync_end);
PSB_DEBUG_ENTRY("htotal is %d\n", mode->htotal);
PSB_DEBUG_ENTRY("VSS is %d\n", mode->vsync_start);
PSB_DEBUG_ENTRY("VSE is %d\n", mode->vsync_end);
PSB_DEBUG_ENTRY("vtotal is %d\n", mode->vtotal);
PSB_DEBUG_ENTRY("clock is %d\n", mode->clock);
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
struct drm_display_mode *nt51021_get_modes(struct intel_dsi_device *dsi)
{
struct drm_display_mode *mode = NULL;
/* Allocate */
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) {
DRM_DEBUG_KMS("AUO B101UAN01E Panel: No memory\n");
return NULL;
}
mode->hdisplay = 1200;
//mode->hsync_start = mode->hdisplay + 100; //fp
//mode->hsync_end = mode->hsync_start + 12; //sync
//mode->htotal = mode->hsync_end + 20; //bp
mode->hsync_start = mode->hdisplay + 42; //fp
mode->hsync_end = mode->hsync_start + 1; //sync
mode->htotal = mode->hsync_end + 32; //bp
mode->vdisplay = 1920;
mode->vsync_start = mode->vdisplay + 35;
mode->vsync_end = mode->vsync_start + 1;
mode->vtotal = mode->vsync_end + 25;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
/* Configure */
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
printk("%s drm debug Loaded mode=%dx%d\n",__func__,
mode->hdisplay, mode->vdisplay);
return mode;
}
bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
struct drm_display_mode *fixed_mode = dsi_config->fixed_mode;
if (fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
return true;
}
static void
gi_renesas_dsi_controller_init(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_context *hw_ctx =
&dsi_config->dsi_hw_context;
struct drm_device *dev = dsi_config->dev;
struct csc_setting csc = { .pipe = 0,
.type = CSC_REG_SETTING,
.enable_state = true,
.data_len = CSC_REG_COUNT,
.data.csc_reg_data = {
0xF510486, 0x27, 0x3F10FD0, 0x3E, 0x51000F, 0x39F}
};
struct gamma_setting gamma = { .pipe = 0,
.type = GAMMA_REG_SETTING,
.enable_state = true,
.data_len = GAMMA_10_BIT_TABLE_COUNT,
.gamma_tableX100 = {
0x000000, 0x010101, 0x020202, 0x030303,
0x040404, 0x050505, 0x060606, 0x070807,
0x080908, 0x0A0B0A, 0x0B0C0B, 0x0D0D0D,
0x0E0F0E, 0x0F100F, 0x111211, 0x121312,
0x141514, 0x151715, 0x171817, 0x191A19,
0x1A1C1A, 0x1C1D1C, 0x1D1F1D, 0x1F211F,
0x212221, 0x222422, 0x242624, 0x262726,
0x272928, 0x292B29, 0x2B2D2B, 0x2D2F2D,
0x2E302F, 0x303230, 0x323432, 0x343634,
0x363836, 0x383A38, 0x393B39, 0x3B3D3B,
0x3D3F3D, 0x3F413F, 0x414341, 0x434543,
0x454745, 0x474947, 0x494B49, 0x4B4D4B,
0x4C4F4D, 0x4E514F, 0x505351, 0x525552,
0x545754, 0x565956, 0x585B58, 0x5A5D5A,
0x5C5F5D, 0x5E615F, 0x606361, 0x636563,
0x656765, 0x676967, 0x696B69, 0x6B6D6B,
0x6D6F6D, 0x6F716F, 0x717371, 0x737573,
0x757775, 0x777A78, 0x7A7C7A, 0x7C7E7C,
0x7E807E, 0x808280, 0x828482, 0x848684,
0x868887, 0x898B89, 0x8B8D8B, 0x8D8F8D,
0x8F918F, 0x919391, 0x949594, 0x969896,
0x989A98, 0x9A9C9A, 0x9D9E9D, 0x9FA09F,
0xA1A3A1, 0xA3A5A3, 0xA5A7A6, 0xA8A9A8,
0xAAACAA, 0xACAEAC, 0xAFB0AF, 0xB1B2B1,
0xB3B5B3, 0xB5B7B5, 0xB8B9B8, 0xBABBBA,
0xBCBEBC, 0xBFC0BF, 0xC1C2C1, 0xC3C5C3,
0xC6C7C6, 0xC8C9C8, 0xCACBCA, 0xCDCECD,
0xCFD0CF, 0xD1D2D1, 0xD4D5D4, 0xD6D7D6,
0xD8D9D8, 0xDBDCDB, 0xDDDEDD, 0xE0E0E0,
0xE2E3E2, 0xE4E5E4, 0xE7E7E7, 0xE9EAE9,
0xECECEC, 0xEEEEEE, 0xF0F1F0, 0xF3F3F3,
0xF5F5F5, 0xF8F8F8, 0xFAFAFA, 0xFDFDFD}
};
PSB_DEBUG_ENTRY("\n");
dsi_config->lane_count = 1;
dsi_config->lane_config = MDFLD_DSI_DATA_LANE_2_2;
dsi_config->enable_gamma_csc = ENABLE_GAMMA | ENABLE_CSC;
hw_ctx->pll_bypass_mode = 1;
hw_ctx->cck_div = 1;
hw_ctx->mipi_control = 0x00;
hw_ctx->intr_en = 0xffffffff;
hw_ctx->hs_tx_timeout = 0xffffff;
hw_ctx->lp_rx_timeout = 0xffffff;
hw_ctx->turn_around_timeout = 0x14;
hw_ctx->device_reset_timer = 0xffff;
hw_ctx->high_low_switch_count = 0x28;
hw_ctx->init_count = 0xf0;
hw_ctx->eot_disable = 0x2;
hw_ctx->hs_ls_dbi_enable = 0x0;
hw_ctx->lp_byteclk = 0x0;
hw_ctx->clk_lane_switch_time_cnt = 0xa0014;
hw_ctx->dphy_param = 0x150a600f;
hw_ctx->dbi_bw_ctrl = 0x820;
hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN;
hw_ctx->mipi |= dsi_config->lane_config;
/*set up func_prg*/
hw_ctx->dsi_func_prg = (0xa000 | dsi_config->lane_count);
if (dsi_config->enable_gamma_csc & ENABLE_CSC) {
/* setting the tuned csc setting */
drm_psb_enable_color_conversion = 1;
mdfld_intel_crtc_set_color_conversion(dev, &csc);
}
if (dsi_config->enable_gamma_csc & ENABLE_GAMMA) {
/* setting the tuned gamma setting */
drm_psb_enable_gamma = 1;
mdfld_intel_crtc_set_gamma(dev, &gamma);
}
}
static
struct drm_display_mode *gi_renesas_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 320;
mode->vdisplay = 480;
/* HFP = 10, HSYNC = 10, HBP = 20 */
mode->hsync_start = mode->hdisplay + 10;
mode->hsync_end = mode->hsync_start + 10;
mode->htotal = mode->hsync_end + 20;
/* VFP = 10, VSYNC = 2, VBP = 20 */
mode->vsync_start = mode->vdisplay + 10;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 10;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static
int __gi_renesas_dsi_power_on(struct mdfld_dsi_config *dsi_config)
{
struct drm_device *dev = dsi_config->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
struct mdfld_dsi_hw_registers *regs =
&dsi_config->regs;
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err = 0;
PSB_DEBUG_ENTRY("\n");
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
if (drm_psb_enable_cabc) {
/* enable cabc */
gi_er61529_backlight_cntr_1[1] = 0x01;
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_backlight_cntr_1, 21, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);
}
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_backlight_cntr, 5, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);
mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_exit_sleep_mode, 1, 0);
mdelay(120);
mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_set_tear_on, 2, 0);
mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_dcs_set_display_on, 1, 0);
return err;
}
static
int __gi_renesas_dsi_power_off(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err = 0;
PSB_DEBUG_ENTRY("Turn off video mode TMD panel...\n");
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
/* turn off display */
err = mdfld_dsi_send_dcs(sender,
set_display_off,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("%s - sent set_display_off faild\n", __func__);
goto power_err;
}
mdelay(70);
/* set tear off display */
err = mdfld_dsi_send_dcs(sender,
set_tear_off,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("%s - sent set_tear_off faild\n", __func__);
goto power_err;
}
/* disable CABC */
gi_er61529_backlight_cntr_1[1] = 0x00;
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_backlight_cntr_1, 21, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);
err =
mdfld_dsi_send_mcs_long_hs(sender, gi_er61529_enter_sleep_mode, 1, 0);
if (err) {
DRM_ERROR("Enter sleep mode error\n");
goto power_err;
}
mdelay(120);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_lp_mode_cntr, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);
power_err:
return err;
}
static
void gi_renesas_cmd_get_panel_info(int pipe, struct panel_info *pi)
{
if (pipe == 0) {
pi->width_mm = PANEL_3DOT47_WIDTH;
pi->height_mm = PANEL_3DOT47_HEIGHT;
}
}
static
int gi_renesas_dsi_cmd_detect(struct mdfld_dsi_config *dsi_config)
{
struct drm_device *dev = dsi_config->dev;
struct mdfld_dsi_hw_registers *regs = &dsi_config->regs;
int status;
int pipe = dsi_config->pipe;
uint32_t dpll_val, device_ready_val;
PSB_DEBUG_ENTRY("\n");
if (pipe == 0) {
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
OSPM_UHB_FORCE_POWER_ON)) {
DRM_ERROR("hw begin failed\n");
return -EAGAIN;
}
dpll_val = REG_READ(regs->dpll_reg);
device_ready_val = REG_READ(regs->device_ready_reg);
if ((device_ready_val & DSI_DEVICE_READY) &&
(dpll_val & DPLL_VCO_ENABLE)) {
dsi_config->dsi_hw_context.panel_on = true;
status = MDFLD_DSI_PANEL_CONNECTED;
} else {
dsi_config->dsi_hw_context.panel_on = false;
status = MDFLD_DSI_PANEL_DISCONNECTED;
DRM_INFO("%s: do NOT support dual panel\n", __func__);
}
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
} else {
PSB_DEBUG_ENTRY("Only support single panel\n");
status = MDFLD_DSI_PANEL_DISCONNECTED;
dsi_config->dsi_hw_context.panel_on = 0;
}
return 0;
}
static
int gi_renesas_dsi_cmd_set_brightness(struct mdfld_dsi_config *dsi_config,
int level)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
u8 backlight_val;
PSB_DEBUG_ENTRY("Set brightness level %d...\n", level);
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
backlight_val = level * 255 / 100;
gi_er61529_set_backlight[2] = backlight_val;
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_on, 2, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_set_backlight, 5, 0);
mdfld_dsi_send_gen_long_hs(sender, gi_er61529_mcs_protect_off, 2, 0);
return 0;
}
static
int gi_renesas_dsi_panel_reset(struct mdfld_dsi_config *dsi_config)
{
static int mipi_reset_gpio;
int ret = 0;
PSB_DEBUG_ENTRY("\n");
if (mipi_reset_gpio == 0) {
ret = get_gpio_by_name("mipi-reset");
if (ret < 0) {
DRM_ERROR("Faild to get panel reset gpio, " \
"use default reset pin\n");
ret = 128;
}
mipi_reset_gpio = ret;
ret = gpio_request(mipi_reset_gpio, "mipi_display");
if (ret) {
DRM_ERROR("Faild to request panel reset gpio\n");
return -EINVAL;
}
gpio_direction_output(mipi_reset_gpio, 0);
}
gpio_set_value_cansleep(mipi_reset_gpio, 0);
mdelay(11);
gpio_set_value_cansleep(mipi_reset_gpio, 1);
mdelay(20);
return 0;
}
void gi_renesas_cmd_init(struct drm_device *dev, struct panel_funcs *p_funcs)
{
p_funcs->get_config_mode = gi_renesas_cmd_get_config_mode;
p_funcs->get_panel_info = gi_renesas_cmd_get_panel_info;
p_funcs->reset = gi_renesas_dsi_panel_reset;
p_funcs->drv_ic_init = gi_renesas_dbi_ic_init;
p_funcs->dsi_controller_init = gi_renesas_dsi_controller_init;
p_funcs->detect = gi_renesas_dsi_cmd_detect;
p_funcs->set_brightness = gi_renesas_dsi_cmd_set_brightness;
p_funcs->power_on = __gi_renesas_dsi_power_on;
p_funcs->power_off = __gi_renesas_dsi_power_off;
}
static
void mdfld_h8c7_dsi_controller_init(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_context *hw_ctx = &dsi_config->dsi_hw_context;
struct drm_device *dev = dsi_config->dev;
struct csc_setting csc = { .pipe = 0,
.type = CSC_REG_SETTING,
.enable_state = true,
.data_len = CSC_REG_COUNT,
.data.csc_reg_data = {
0xFFB0424, 0xFDF, 0x4320FF1, 0xFDC, 0xFF50FF5, 0x415}
};
struct gamma_setting gamma = { .pipe = 0,
.type = GAMMA_REG_SETTING,
.enable_state = true,
.data_len = GAMMA_10_BIT_TABLE_COUNT,
.gamma_tableX100 = {
0x000000, 0x030303, 0x050505, 0x070707,
0x090909, 0x0C0C0C, 0x0E0E0E, 0x101010,
0x121212, 0x141414, 0x171717, 0x191919,
0x1B1B1B, 0x1D1D1D, 0x1F1F1F, 0x212121,
0x232323, 0x252525, 0x282828, 0x2A2A2A,
0x2C2C2C, 0x2E2E2E, 0x303030, 0x323232,
0x343434, 0x363636, 0x383838, 0x3A3A3A,
0x3C3C3C, 0x3E3E3E, 0x404040, 0x424242,
0x444444, 0x464646, 0x484848, 0x4A4A4A,
0x4C4C4C, 0x4E4E4E, 0x505050, 0x525252,
0x545454, 0x565656, 0x585858, 0x5A5A5A,
0x5C5C5C, 0x5E5E5E, 0x606060, 0x626262,
0x646464, 0x666666, 0x686868, 0x6A6A6A,
0x6C6C6C, 0x6E6E6E, 0x707070, 0x727272,
0x747474, 0x767676, 0x787878, 0x7A7A7A,
0x7C7C7C, 0x7E7E7E, 0x808080, 0x828282,
0x848484, 0x868686, 0x888888, 0x8A8A8A,
0x8C8C8C, 0x8E8E8E, 0x909090, 0x929292,
0x949494, 0x969696, 0x989898, 0x999999,
0x9B9B9B, 0x9D9D9D, 0x9F9F9F, 0xA1A1A1,
0xA3A3A3, 0xA5A5A5, 0xA7A7A7, 0xA9A9A9,
0xABABAB, 0xADADAD, 0xAFAFAF, 0xB1B1B1,
0xB3B3B3, 0xB5B5B5, 0xB6B6B6, 0xB8B8B8,
0xBABABA, 0xBCBCBC, 0xBEBEBE, 0xC0C0C0,
0xC2C2C2, 0xC4C4C4, 0xC6C6C6, 0xC8C8C8,
0xCACACA, 0xCCCCCC, 0xCECECE, 0xCFCFCF,
0xD1D1D1, 0xD3D3D3, 0xD5D5D5, 0xD7D7D7,
0xD9D9D9, 0xDBDBDB, 0xDDDDDD, 0xDFDFDF,
0xE1E1E1, 0xE3E3E3, 0xE4E4E4, 0xE6E6E6,
0xE8E8E8, 0xEAEAEA, 0xECECEC, 0xEEEEEE,
0xF0F0F0, 0xF2F2F2, 0xF4F4F4, 0xF6F6F6,
0xF7F7F7, 0xF9F9F9, 0xFBFBFB, 0xFDFDFD}
};
PSB_DEBUG_ENTRY("\n");
/*reconfig lane configuration*/
dsi_config->lane_count = 3;
dsi_config->lane_config = MDFLD_DSI_DATA_LANE_3_1;
dsi_config->enable_gamma_csc = ENABLE_GAMMA | ENABLE_CSC;
/* This is for 400 mhz. Set it to 0 for 800mhz */
hw_ctx->cck_div = 1;
hw_ctx->pll_bypass_mode = 0;
hw_ctx->mipi_control = 0x00;
hw_ctx->intr_en = 0xffffffff;
hw_ctx->hs_tx_timeout = 0xffffff;
hw_ctx->lp_rx_timeout = 0xffffff;
hw_ctx->turn_around_timeout = 0x1f;
hw_ctx->device_reset_timer = 0xffff;
hw_ctx->high_low_switch_count = 0x20;
hw_ctx->init_count = 0xf0;
hw_ctx->eot_disable = 0x3;
hw_ctx->lp_byteclk = 0x4;
hw_ctx->clk_lane_switch_time_cnt = 0x20000E;
hw_ctx->hs_ls_dbi_enable = 0x0;
/* HW team suggested 1390 for bandwidth setting */
hw_ctx->dbi_bw_ctrl = 1390;
hw_ctx->dphy_param = 0x20124E1A;
hw_ctx->dsi_func_prg = (0xa000 | dsi_config->lane_count);
hw_ctx->mipi = TE_TRIGGER_GPIO_PIN;
hw_ctx->mipi |= dsi_config->lane_config;
if (dsi_config->enable_gamma_csc & ENABLE_CSC) {
/* setting the tuned csc setting */
drm_psb_enable_color_conversion = 1;
mdfld_intel_crtc_set_color_conversion(dev, &csc);
}
if (dsi_config->enable_gamma_csc & ENABLE_GAMMA) {
/* setting the tuned gamma setting */
drm_psb_enable_gamma = 1;
mdfld_intel_crtc_set_gamma(dev, &gamma);
}
}
static
struct drm_display_mode *h8c7_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->htotal = 920;
mode->hdisplay = 720;
mode->hsync_start = 816;
mode->hsync_end = 824;
mode->vtotal = 1300;
mode->vdisplay = 1280;
mode->vsync_start = 1294;
mode->vsync_end = 1296;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
PSB_DEBUG_ENTRY("hdisplay is %d\n", mode->hdisplay);
PSB_DEBUG_ENTRY("vdisplay is %d\n", mode->vdisplay);
PSB_DEBUG_ENTRY("HSS is %d\n", mode->hsync_start);
PSB_DEBUG_ENTRY("HSE is %d\n", mode->hsync_end);
PSB_DEBUG_ENTRY("htotal is %d\n", mode->htotal);
PSB_DEBUG_ENTRY("VSS is %d\n", mode->vsync_start);
PSB_DEBUG_ENTRY("VSE is %d\n", mode->vsync_end);
PSB_DEBUG_ENTRY("vtotal is %d\n", mode->vtotal);
PSB_DEBUG_ENTRY("clock is %d\n", mode->clock);
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static
int mdfld_dsi_h8c7_cmd_power_on(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err = 0;
int enable_err, enabled = 0;
PSB_DEBUG_ENTRY("\n");
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
if (!IS_ERR(h8c7_regulator_status.regulator)) {
if (!h8c7_regulator_status.h8c7_mmc2_on) {
PSB_DEBUG_ENTRY("Before power on, regulator is %d\n",
regulator_is_enabled(h8c7_regulator_status.regulator));
PSB_DEBUG_ENTRY("Begin to power on\n");
h8c7_regulator_status.h8c7_mmc2_on = true;
} else {
DRM_ERROR("power on several times without off\n");
}
enabled = regulator_is_enabled(h8c7_regulator_status.regulator);
enable_err = regulator_enable(h8c7_regulator_status.regulator);
if (enable_err < 0) {
regulator_put(h8c7_regulator_status.regulator);
DRM_ERROR("FATAL:enable h8c7 regulator error\n");
}
/* vemmc2 need 50ms delay due to stability
** If already enabled, no need to wait for this delay.
** This code isn't race proof but since in addition to
** this panel driver only touch driver is enabling this
** regulator and does it after this function has been
** finished, this code works well enough for now.
*/
if (!enabled)
msleep(50);
PSB_DEBUG_ENTRY("After power on, regulator is %d\n",
regulator_is_enabled(h8c7_regulator_status.regulator));
}
/*exit sleep */
err = mdfld_dsi_send_dcs(sender,
exit_sleep_mode,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("faild to exit_sleep mode\n");
goto power_err;
}
msleep(120);
/*set tear on*/
err = mdfld_dsi_send_dcs(sender,
set_tear_on,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("faild to set_tear_on mode\n");
goto power_err;
}
/*turn on display*/
err = mdfld_dsi_send_dcs(sender,
set_display_on,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("faild to set_display_on mode\n");
goto power_err;
}
if (drm_psb_enable_cabc) {
/* turn on cabc */
h8c7_disable_cabc[1] = 0x2;
mdfld_dsi_send_mcs_long_hs(sender, h8c7_disable_cabc,
sizeof(h8c7_disable_cabc), 0);
mdelay(5);
mdfld_dsi_send_gen_long_hs(sender, h8c7_mcs_protect_off, 4, 0);
mdfld_dsi_send_mcs_long_hs(sender, h8c7_set_cabc_gain, 10, 0);
mdfld_dsi_send_gen_long_hs(sender, h8c7_mcs_protect_on, 4, 0);
DRM_INFO("%s enable h8c7 cabc\n", __func__);
}
power_err:
return err;
}
static int mdfld_dsi_h8c7_cmd_power_off(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err = 0;
PSB_DEBUG_ENTRY("\n");
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
/* turn off cabc */
h8c7_disable_cabc[1] = 0x0;
mdfld_dsi_send_mcs_long_lp(sender, h8c7_disable_cabc,
sizeof(h8c7_disable_cabc), 0);
/*turn off backlight*/
err = mdfld_dsi_send_mcs_long_lp(sender, h8c7_turn_off_backlight,
sizeof(h8c7_turn_off_backlight), 0);
if (err) {
DRM_ERROR("%s: failed to turn off backlight\n", __func__);
goto out;
}
mdelay(1);
/*turn off display */
err = mdfld_dsi_send_dcs(sender,
set_display_off,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("sent set_display_off faild\n");
goto out;
}
/*set tear off */
err = mdfld_dsi_send_dcs(sender,
set_tear_off,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("sent set_tear_off faild\n");
goto out;
}
/*Enter sleep mode */
err = mdfld_dsi_send_dcs(sender,
enter_sleep_mode,
NULL,
0,
CMD_DATA_SRC_SYSTEM_MEM,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("DCS 0x%x sent failed\n", enter_sleep_mode);
goto out;
}
/**
* MIPI spec shows it must wait 5ms
* before sneding next command
*/
mdelay(5);
/*enter deep standby mode*/
err = mdfld_dsi_send_mcs_long_lp(sender, h8c7_mcs_protect_off, 4, 0);
if (err) {
DRM_ERROR("Failed to turn off protection\n");
goto out;
}
err = mdfld_dsi_send_mcs_long_lp(sender, h8c7_set_power_dstb, 14, 0);
if (err)
DRM_ERROR("Failed to enter DSTB\n");
mdelay(5);
mdfld_dsi_send_mcs_long_lp(sender, h8c7_mcs_protect_on, 4, 0);
out:
if (!IS_ERR(h8c7_regulator_status.regulator)) {
if (h8c7_regulator_status.h8c7_mmc2_on) {
h8c7_regulator_status.h8c7_mmc2_on = false;
PSB_DEBUG_GENERAL("Begin to power off\n");
} else
DRM_ERROR("power off several times without on\n");
regulator_disable(h8c7_regulator_status.regulator);
PSB_DEBUG_GENERAL("After power off, regulator is %d\n",
regulator_is_enabled(h8c7_regulator_status.regulator));
}
return err;
}
static
void h8c7_cmd_get_panel_info(int pipe, struct panel_info *pi)
{
PSB_DEBUG_ENTRY("\n");
if (pipe == 0) {
pi->width_mm = PANEL_4DOT3_WIDTH;
pi->height_mm = PANEL_4DOT3_HEIGHT;
}
}
static
int mdfld_dsi_h8c7_cmd_detect(struct mdfld_dsi_config *dsi_config)
{
int status;
struct drm_device *dev = dsi_config->dev;
struct mdfld_dsi_hw_registers *regs = &dsi_config->regs;
u32 dpll_val, device_ready_val;
int pipe = dsi_config->pipe;
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
PSB_DEBUG_ENTRY("\n");
if (pipe == 0) {
/*
* FIXME: WA to detect the panel connection status, and need to
* implement detection feature with get_power_mode DSI command.
*/
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
OSPM_UHB_FORCE_POWER_ON)) {
DRM_ERROR("hw begin failed\n");
return -EAGAIN;
}
dpll_val = REG_READ(regs->dpll_reg);
device_ready_val = REG_READ(regs->device_ready_reg);
if ((device_ready_val & DSI_DEVICE_READY) &&
(dpll_val & DPLL_VCO_ENABLE)) {
dsi_config->dsi_hw_context.panel_on = true;
mdfld_dsi_send_gen_long_hs(sender, h8c7_mcs_protect_off, 4, 0);
mdfld_dsi_send_gen_long_hs(sender, h8c7_set_disp_reg, 13, 0);
mdfld_dsi_send_gen_long_hs(sender, h8c7_mcs_protect_on, 4, 0);
} else {
dsi_config->dsi_hw_context.panel_on = false;
DRM_INFO("%s: panel is not initialized!\n", __func__);
}
status = MDFLD_DSI_PANEL_CONNECTED;
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
} else {
DRM_INFO("%s: do NOT support dual panel\n", __func__);
status = MDFLD_DSI_PANEL_DISCONNECTED;
}
return status;
}
struct drm_display_mode *otm1284a_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
printk("[DISP] %s\n", __func__);
if (lcd_id == ZE500ML_HSD) {
/* RECOMMENDED PORCH SETTING
HSA=18, HBP=48, HFP=64
VSA=3, VBP=14, VFP=9 Orise*/
mode->hdisplay = 720;
mode->hsync_start = mode->hdisplay + 64;
mode->hsync_end = mode->hsync_start + 18;
mode->htotal = mode->hsync_end + 48;
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 9;
mode->vsync_end = mode->vsync_start + 3;
mode->vtotal = mode->vsync_end + 14;
} else if (lcd_id == ZE500ML_CTP || lcd_id == ZE550ML_CPT) {
/* RECOMMENDED PORCH SETTING
HSA=2, HBP=10, HFP=10
VSA=2, VBP=10, VFP=10 Orise*/
mode->hdisplay = 720;
mode->hsync_start = mode->hdisplay + 10;
mode->hsync_end = mode->hsync_start + 2;
mode->htotal = mode->hsync_end + 10;
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 10;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 10;
} else if (lcd_id == ZE550ML_TM || lcd_id == ZE550ML_TM_SR || lcd_id == ZE550ML_TM_MP) {
/* RECOMMENDED PORCH SETTING
HSA=12, HBP=64, HFP=64
VSA=5, VBP=13, VFP=10 Orise*/
mode->hdisplay = 720;
mode->hsync_start = mode->hdisplay + 64;
mode->hsync_end = mode->hsync_start + 12;
mode->htotal = mode->hsync_end + 64;
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 10;
mode->vsync_end = mode->vsync_start + 5;
mode->vtotal = mode->vsync_end + 13;
} else { //TM
/* RECOMMENDED PORCH SETTING
HSA=2, HBP=42, HFP=44
VSA=2, VBP=14, VFP=16 Orise*/
mode->hdisplay = 720;
mode->hsync_start = mode->hdisplay + 44;
mode->hsync_end = mode->hsync_start + 2;
mode->htotal = mode->hsync_end + 42;
mode->vdisplay = 1280;
mode->vsync_start = mode->vdisplay + 16;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 14;
}
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
struct drm_display_mode *h8c7_get_config_mode(struct drm_device *dev)
{
struct drm_display_mode *mode;
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;
struct mrst_timing_info *ti = &dev_priv->gct_data.DTD;
bool use_gct = false; /*Disable GCT for now*/
if (IS_CTP(dev))
use_gct = true;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
if (use_gct) {
PSB_DEBUG_ENTRY("gct find MIPI panel.\n");
mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
mode->hsync_start = mode->hdisplay + \
((ti->hsync_offset_hi << 8) | \
ti->hsync_offset_lo);
mode->hsync_end = mode->hsync_start + \
((ti->hsync_pulse_width_hi << 8) | \
ti->hsync_pulse_width_lo);
mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
ti->hblank_lo);
mode->vsync_start = \
mode->vdisplay + ((ti->vsync_offset_hi << 8) | \
ti->vsync_offset_lo);
mode->vsync_end = \
mode->vsync_start + ((ti->vsync_pulse_width_hi << 8) | \
ti->vsync_pulse_width_lo);
mode->vtotal = mode->vdisplay + \
((ti->vblank_hi << 8) | ti->vblank_lo);
mode->clock = ti->pixel_clock * 10;
PSB_DEBUG_ENTRY("hdisplay is %d\n", mode->hdisplay);
PSB_DEBUG_ENTRY("vdisplay is %d\n", mode->vdisplay);
PSB_DEBUG_ENTRY("HSS is %d\n", mode->hsync_start);
PSB_DEBUG_ENTRY("HSE is %d\n", mode->hsync_end);
PSB_DEBUG_ENTRY("htotal is %d\n", mode->htotal);
PSB_DEBUG_ENTRY("VSS is %d\n", mode->vsync_start);
PSB_DEBUG_ENTRY("VSE is %d\n", mode->vsync_end);
PSB_DEBUG_ENTRY("vtotal is %d\n", mode->vtotal);
PSB_DEBUG_ENTRY("clock is %d\n", mode->clock);
} else {
mode->hdisplay = 720;
mode->vdisplay = 1280;
mode->hsync_start = 816;
mode->hsync_end = 824;
mode->htotal = 920;
mode->vsync_start = 1284;
mode->vsync_end = 1286;
mode->vtotal = 1300;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
}
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
struct intel_crtc_config *pipe_config,
int fitting_mode)
{
struct drm_device *dev = intel_crtc->base.dev;
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
struct drm_display_mode *mode, *adjusted_mode;
mode = &pipe_config->requested_mode;
adjusted_mode = &pipe_config->adjusted_mode;
/* Native modes don't need fitting */
if (adjusted_mode->hdisplay == mode->hdisplay &&
adjusted_mode->vdisplay == mode->vdisplay)
goto out;
drm_mode_set_crtcinfo(adjusted_mode, 0);
pipe_config->timings_set = true;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
/*
* For centered modes, we have to calculate border widths &
* heights and modify the values programmed into the CRTC.
*/
centre_horizontally(adjusted_mode, mode->hdisplay);
centre_vertically(adjusted_mode, mode->vdisplay);
border = LVDS_BORDER_ENABLE;
break;
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
if (INTEL_INFO(dev)->gen >= 4) {
u32 scaled_width = adjusted_mode->hdisplay *
mode->vdisplay;
u32 scaled_height = mode->hdisplay *
adjusted_mode->vdisplay;
/* 965+ is easy, it does everything in hw */
if (scaled_width > scaled_height)
pfit_control |= PFIT_ENABLE |
PFIT_SCALING_PILLAR;
else if (scaled_width < scaled_height)
pfit_control |= PFIT_ENABLE |
PFIT_SCALING_LETTER;
else if (adjusted_mode->hdisplay != mode->hdisplay)
pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
} else {
u32 scaled_width = adjusted_mode->hdisplay *
mode->vdisplay;
u32 scaled_height = mode->hdisplay *
adjusted_mode->vdisplay;
/*
* For earlier chips we have to calculate the scaling
* ratio by hand and program it into the
* PFIT_PGM_RATIO register
*/
if (scaled_width > scaled_height) { /* pillar */
centre_horizontally(adjusted_mode,
scaled_height /
mode->vdisplay);
border = LVDS_BORDER_ENABLE;
if (mode->vdisplay != adjusted_mode->vdisplay) {
u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
bits << PFIT_VERT_SCALE_SHIFT);
pfit_control |= (PFIT_ENABLE |
VERT_INTERP_BILINEAR |
HORIZ_INTERP_BILINEAR);
}
} else if (scaled_width < scaled_height) { /* letter */
centre_vertically(adjusted_mode,
scaled_width /
mode->hdisplay);
border = LVDS_BORDER_ENABLE;
if (mode->hdisplay != adjusted_mode->hdisplay) {
u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
bits << PFIT_VERT_SCALE_SHIFT);
pfit_control |= (PFIT_ENABLE |
VERT_INTERP_BILINEAR |
HORIZ_INTERP_BILINEAR);
}
} else {
/* Aspects match, Let hw scale both directions */
pfit_control |= (PFIT_ENABLE |
VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
VERT_INTERP_BILINEAR |
HORIZ_INTERP_BILINEAR);
}
}
break;
case DRM_MODE_SCALE_FULLSCREEN:
/*
* Full scaling, even if it changes the aspect ratio.
* Fortunately this is all done for us in hw.
*/
if (mode->vdisplay != adjusted_mode->vdisplay ||
mode->hdisplay != adjusted_mode->hdisplay) {
pfit_control |= PFIT_ENABLE;
if (INTEL_INFO(dev)->gen >= 4)
pfit_control |= PFIT_SCALING_AUTO;
else
pfit_control |= (VERT_AUTO_SCALE |
VERT_INTERP_BILINEAR |
HORIZ_AUTO_SCALE |
HORIZ_INTERP_BILINEAR);
}
break;
default:
WARN(1, "bad panel fit mode: %d\n", fitting_mode);
return;
}
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
if (INTEL_INFO(dev)->gen >= 4)
pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
PFIT_FILTER_FUZZY);
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
pfit_control = 0;
pfit_pgm_ratios = 0;
}
/* Make sure pre-965 set dither correctly for 18bpp panels. */
if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
pipe_config->gmch_pfit.control = pfit_control;
pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
pipe_config->gmch_pfit.lvds_border_bits = border;
}
