int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mdp_clock_init();
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_clock_auto_pll_init(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
// * Add here for continuous splash *
mmss_clock_disable(dual_dsi);
mdp_clock_disable(dual_dsi);
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
int32_t ret;
struct mdss_dsi_pll_config *pll_data;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clocks_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clocks_enable(pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
mmss_dsi_clocks_disable();
mdp_clock_disable();
mmss_bus_clocks_disable();
mdp_gdsc_ctrl(enable);
}
return 0;
}
int target_backlight_ctrl(uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.function = PM_GPIO_FUNC_1,
.vin_sel = 2, /* VIN_2 */
.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
if (enable) {
pm8x41_gpio_config(7, &pwmgpio_param);
/* lpg channel 2 */
pm8x41_lpg_write(3, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(3, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(3, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
pm8x41_lpg_write(3, 0x44, 0xcc); /* LPG_VALUE_LSB */
pm8x41_lpg_write(3, 0x45, 0x00); /* LPG_VALUE_MSB */
pm8x41_lpg_write(3, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
pm8x41_lpg_write(3, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
mdss_dsi_auto_pll_config(MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI0_BASE);
if (pinfo->mipi.dual_dsi &&
!(pinfo->mipi.broadcast)) {
mdss_dsi_auto_pll_config(MIPI_DSI1_BASE, pll_data);
dsi_pll_enable_seq(MIPI_DSI1_BASE);
}
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
mmss_dsi_clock_disable(dual_dsi);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
/* Pull DISP_RST_N high to get panel out of reset */
int target_panel_reset(uint8_t enable, struct panel_reset_sequence *resetseq,
struct msm_panel_info *pinfo)
{
uint32_t i = 0;
if (enable) {
gpio_tlmm_config(reset_gpio.pin_id, 0,
reset_gpio.pin_direction, reset_gpio.pin_pull,
reset_gpio.pin_strength, reset_gpio.pin_state);
gpio_tlmm_config(enable_gpio.pin_id, 0,
enable_gpio.pin_direction, enable_gpio.pin_pull,
enable_gpio.pin_strength, enable_gpio.pin_state);
gpio_tlmm_config(bkl_gpio.pin_id, 0,
bkl_gpio.pin_direction, bkl_gpio.pin_pull,
bkl_gpio.pin_strength, bkl_gpio.pin_state);
gpio_set(enable_gpio.pin_id, 2);
gpio_set(bkl_gpio.pin_id, 2);
/* reset */
for (i = 0; i < RESET_GPIO_SEQ_LEN; i++) {
if (resetseq->pin_state[i] == GPIO_STATE_LOW)
gpio_set(reset_gpio.pin_id, GPIO_STATE_LOW);
else
gpio_set(reset_gpio.pin_id, GPIO_STATE_HIGH);
mdelay(resetseq->sleep[i]);
}
} else {
gpio_set(reset_gpio.pin_id, 0);
gpio_set(enable_gpio.pin_id, 0);
gpio_set(bkl_gpio.pin_id, 0);
}
return NO_ERROR;
}
int target_backlight_ctrl(struct backlight *bl, uint8_t enable)
{
struct pm8x41_gpio pwmgpio_param = {
.direction = PM_GPIO_DIR_OUT,
.function = PM_GPIO_FUNC_1,
.vin_sel = 2, /* VIN_2 */
.pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10,
.output_buffer = PM_GPIO_OUT_CMOS,
.out_strength = 0x03,
};
if (enable) {
pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param);
/* lpg channel 3 */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */
} else {
pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */
}
return NO_ERROR;
}
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
{
uint32_t ret;
struct mdss_dsi_pll_config *pll_data;
uint32_t dual_dsi = pinfo->mipi.dual_dsi;
dprintf(SPEW, "target_panel_clock\n");
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
mdp_gdsc_ctrl(enable);
mmss_bus_clock_enable();
mdp_clock_enable();
ret = restore_secure_cfg(SECURE_DEVICE_MDSS);
if (ret) {
dprintf(CRITICAL,
"%s: Failed to restore MDP security configs",
__func__);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(0);
return ret;
}
mdss_dsi_auto_pll_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_enable_seq(DSI0_PLL_BASE);
mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
mmss_dsi_clock_disable(dual_dsi);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);
}
return NO_ERROR;
}
