u32 dsim_reg_is_hs_clk_ready(u32 id)
{
if (dsim_read(id, DSIM_STATUS) & DSIM_STATUS_TX_READY_HS_CLK)
return 1;
return 0;
}
u32 dsim_reg_is_noncontinuous_clk_enabled(u32 id)
{
if (dsim_read(id, DSIM_CONFIG) & DSIM_CONFIG_NONCONTINUOUS_CLOCK_LANE)
return 1;
return 0;
}
static u32 dsim_reg_is_hs_clk_ready(void)
{
if (dsim_read(DSIM_STATUS) & DSIM_STATUS_TX_READY_HS_CLK)
return 1;
return 0;
}
static u32 dsim_reg_is_not_ulps_state(u32 id)
{
u32 val = dsim_read(id, DSIM_STATUS);
if (!(DSIM_STATUS_ULPS_DATA_LANE_GET(val))
&& !(val & DSIM_STATUS_ULPS_CLK))
return 1;
return 0;
}
u32 dsim_reg_is_pll_stable(u32 id)
{
u32 val;
val = dsim_read(id, DSIM_STATUS);
if (val & DSIM_STATUS_PLL_STABLE)
return 1;
return 0;
}
void dsim_reg_set_clear_rx_fifo(void)
{
int i;
unsigned int rx_fifo;
for (i = 0; i < DSIM_MAX_RX_FIFO; i++)
rx_fifo = dsim_read(DSIM_RXFIFO);
dsim_info("%s: rx_fifo 0x%08X\n", __func__, rx_fifo);
}
static u32 dsim_reg_is_ulps_state(u32 id, u32 lanes)
{
u32 val = dsim_read(id, DSIM_STATUS);
u32 data_lane = lanes >> DSIM_LANE_CLOCK;
if ((DSIM_STATUS_ULPS_DATA_LANE_GET(val) == data_lane)
&& (val & DSIM_STATUS_ULPS_CLK))
return 1;
return 0;
}
u32 dsim_reg_is_pll_enabled(u32 id)
{
u32 val;
val = dsim_read(id, DSIM_PLLCTRL);
if (val & DSIM_PLLCTRL_PLL_EN)
return 1;
return 0;
}
static u32 dsim_reg_is_lane_stop_state(u32 id)
{
u32 val = dsim_read(id, DSIM_STATUS);
/**
* check clock and data lane states.
* if MIPI-DSI controller was enabled at bootloader then
* TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
* so it should be checked for two case.
*/
if ((val & DSIM_STATUS_STOP_STATE_DAT(0xf)) &&
((val & DSIM_STATUS_STOP_STATE_CLK) || (val & DSIM_STATUS_TX_READY_HS_CLK)))
return 1;
return 0;
}
static u32 dsim_reg_is_lane_stop_state(u32 lanes)
{
u32 val = dsim_read(DSIM_STATUS);
u32 data_lane = lanes >> DSIM_LANE_CLOCK;
/**
* check clock and data lane states.
* if MIPI-DSI controller was enabled at bootloader then
* TX_READY_HS_CLK is enabled otherwise STOP_STATE_CLK.
* so it should be checked for two case.
*/
if ((DSIM_STATUS_STOP_STATE_DATA_LANE_GET(val) == data_lane) &&
((val & DSIM_STATUS_STOP_STATE_CLK) || (val & DSIM_STATUS_TX_READY_HS_CLK)))
return 1;
return 0;
}
u32 dsim_reg_get_hozval(u32 id)
{
u32 val = dsim_read(id, DSIM_MDRESOL);
return DSIM_MDRESOL_HOZVAL_GET(val);
}
u32 dsim_reg_get_lineval(u32 id)
{
u32 val = dsim_read(id, DSIM_MDRESOL);
return DSIM_MDRESOL_LINEVAL_GET(val);
}
int dsim_reg_get_pkt_go_status(void)
{
return (dsim_read(DSIM_MULTI_PKT) & DSIM_PKT_GO_EN) ? 1 : 0;
}
