static void riddle_mute(t_riddle *rd, t_signal **sp)
{
int i, j, nouts = obj_nsigoutlets((t_object *)rd);
t_rdsink *si = rd->rd_outslots;
#ifdef RIDDLE_DEBUG
riddlebug_post(rd, "MUTE", 0);
#endif
if (rd->rd_nsigoutlets != nouts)
{
loudbug_bug("riddle_mute");
riddle_validatesinks(rd);
if (rd->rd_nsigoutlets != nouts)
return;
}
i = 0;
j = obj_nsiginlets((t_object *)rd);
while (nouts--)
{
si->si_pattern = 0;
si->si_block = sp[j]->s_n;
si->si_outbuf[1].a_w.w_symbol = rdps__;
si->si_outbuf[2].a_w.w_float = (t_float)si->si_block;
si->si_isready = 1;
dsp_add_zero(sp[j]->s_vec, sp[j]->s_n);
i++;
j++;
si++;
}
}
static void sigrfft_dsp(t_sigrfft *x, t_signal **sp)
{
int n = sp[0]->s_n, n2 = (n>>1);
t_sample *in1 = sp[0]->s_vec;
t_sample *out1 = sp[1]->s_vec;
t_sample *out2 = sp[2]->s_vec;
if (n < 4)
{
error("fft: minimum 4 points");
return;
}
if (in1 != out1)
dsp_add(copy_perform, 3, in1, out1, n);
dsp_add(sigrfft_perform, 2, out1, n);
dsp_add(sigrfft_flip, 3, out1 + (n2+1), out2 + n2, n2-1);
dsp_add_zero(out1 + (n2+1), ((n2-1)&(~7)));
dsp_add_zero(out1 + (n2+1) + ((n2-1)&(~7)), ((n2-1)&7));
dsp_add_zero(out2 + n2, n2);
dsp_add_zero(out2, 1);
}
static void adc_dsp(t_adc *x, t_signal **sp)
{
t_int i, *ip;
t_signal **sp2;
for (i = x->x_n, ip = x->x_vec, sp2 = sp; i--; ip++, sp2++)
{
int ch = *ip - 1;
if ((*sp2)->s_n != DEFDACBLKSIZE)
error("adc~: bad vector size");
else if (ch >= 0 && ch < sys_get_inchannels())
dsp_add_copy(sys_soundin + DEFDACBLKSIZE*ch,
(*sp2)->s_vec, DEFDACBLKSIZE);
else dsp_add_zero((*sp2)->s_vec, DEFDACBLKSIZE);
}
}
/* set up epilog DSP code. If we're reblocking, this is the
time to copy the samples out to the containing object's outlets.
If we aren't reblocking, there's nothing to do here. */
void voutlet_dspepilog(struct _voutlet *x, t_signal **parentsigs,
int myvecsize, int calcsize, int phase, int period, int frequency,
int downsample, int upsample, int reblock, int switched)
{
if (!x->x_buf) return; /* this shouldn't be necesssary... */
x->x_updown.downsample=downsample;
x->x_updown.upsample=upsample;
if (reblock)
{
t_signal *insig, *outsig;
int parentvecsize, bufsize, oldbufsize;
int re_parentvecsize;
int bigperiod, epilogphase, blockphase;
if (parentsigs)
{
outsig = parentsigs[outlet_getsignalindex(x->x_parentoutlet)];
parentvecsize = outsig->s_vecsize;
re_parentvecsize = parentvecsize * upsample / downsample;
}
else
{
outsig = 0;
parentvecsize = 1;
re_parentvecsize = 1;
}
bigperiod = myvecsize/re_parentvecsize;
if (!bigperiod) bigperiod = 1;
epilogphase = phase & (bigperiod - 1);
blockphase = (phase + period - 1) & (bigperiod - 1) & (- period);
bufsize = re_parentvecsize;
if (bufsize < myvecsize) bufsize = myvecsize;
if (bufsize != (oldbufsize = x->x_bufsize))
{
t_sample *buf = x->x_buf;
t_freebytes(buf, oldbufsize * sizeof(*buf));
buf = (t_sample *)t_getbytes(bufsize * sizeof(*buf));
memset((char *)buf, 0, bufsize * sizeof(*buf));
x->x_bufsize = bufsize;
x->x_endbuf = buf + bufsize;
x->x_buf = buf;
}
if (re_parentvecsize * period > bufsize) bug("voutlet_dspepilog");
x->x_write = x->x_buf + re_parentvecsize * blockphase;
if (x->x_write == x->x_endbuf) x->x_write = x->x_buf;
if (period == 1 && frequency > 1)
x->x_hop = re_parentvecsize / frequency;
else x->x_hop = period * re_parentvecsize;
/* post("phase %d, block %d, parent %d", phase & 63,
parentvecsize * blockphase, parentvecsize * epilogphase); */
if (parentsigs)
{
/* set epilog pointer and schedule it */
x->x_empty = x->x_buf + re_parentvecsize * epilogphase;
if (upsample * downsample == 1)
dsp_add(voutlet_doepilog, 3, x, outsig->s_vec,
re_parentvecsize);
else
{
int method = (x->x_updown.method == 3?
(pd_compatibilitylevel < 44 ? 0 : 1) : x->x_updown.method);
dsp_add(voutlet_doepilog_resampling, 2, x, re_parentvecsize);
resampleto_dsp(&x->x_updown, outsig->s_vec, re_parentvecsize,
parentvecsize, method);
}
}
}
/* if we aren't blocked but we are switched, the epilog code just
copies zeros to the output. In this case the blocking code actually
jumps over the epilog if the block is running. */
else if (switched)
{
if (parentsigs)
{
t_signal *outsig =
parentsigs[outlet_getsignalindex(x->x_parentoutlet)];
dsp_add_zero(outsig->s_vec, outsig->s_n);
}
}
}
