void dss_sdi_enable(void) { dispc_pck_free_enable(1); /* Reset SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ udelay(1); /* wait 2x PCLK */ /* Lock SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ /* Waiting for PLL lock request to complete */ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) ; /* Clearing PLL_GO bit */ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); /* Waiting for PLL to lock */ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) ; dispc_lcd_enable_signal(1); /* Waiting for SDI reset to complete */ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) ; }
int dss_sdi_enable(void) { unsigned long timeout; dispc_pck_free_enable(1); /* Reset SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ udelay(1); /* wait 2x PCLK */ /* Lock SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ /* Waiting for PLL lock request to complete */ timeout = jiffies + msecs_to_jiffies(500); while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { if (time_after_eq(jiffies, timeout)) { DSSERR("PLL lock request timed out\n"); goto err1; } } /* Clearing PLL_GO bit */ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); /* Waiting for PLL to lock */ timeout = jiffies + msecs_to_jiffies(500); while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { if (time_after_eq(jiffies, timeout)) { DSSERR("PLL lock timed out\n"); goto err1; } } dispc_lcd_enable_signal(1); /* Waiting for SDI reset to complete */ timeout = jiffies + msecs_to_jiffies(500); while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { if (time_after_eq(jiffies, timeout)) { DSSERR("SDI reset timed out\n"); goto err2; } } return 0; err2: dispc_lcd_enable_signal(0); err1: /* Reset SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ dispc_pck_free_enable(0); return -ETIMEDOUT; }
int dss_init(bool skip_init) { int r; u32 rev; dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } if (!skip_init) { /* disable LCD and DIGIT output. This seems to fix the synclost * problem that we get, if the bootloader starts the DSS and * the kernel resets it */ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); /* We need to wait here a bit, otherwise we sometimes start to * get synclost errors, and after that only power cycle will * restore DSS functionality. I have no idea why this happens. * And we have to wait _before_ resetting the DSS, but after * enabling clocks. */ msleep(50); _omap_dss_reset(); } /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); return 0; fail1: iounmap(dss.base); fail0: return r; }
void dss_select_clk_source(bool dsi, bool dispc) { u32 r; r = dss_read_reg(DSS_CONTROL); r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */ dss_write_reg(DSS_CONTROL, r); }
static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) { u32 irqstatus; irqstatus = dss_read_reg(DSS_IRQSTATUS); if (irqstatus & (1<<0)) /* DISPC_IRQ */ dispc_irq_handler(); #ifdef CONFIG_OMAP2_DSS_DSI if (irqstatus & (1<<1)) /* DSI_IRQ */ dsi_irq_handler(); #endif /* Workaround suggested by Tony for spurious interrupt warning */ irqstatus = dss_read_reg(DSS_IRQSTATUS); return IRQ_HANDLED; }
void dss_sdi_init(u8 datapairs) { u32 l; BUG_ON(datapairs > 3 || datapairs < 1); l = dss_read_reg(DSS_SDI_CONTROL); l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ dss_write_reg(DSS_SDI_CONTROL, l); l = dss_read_reg(DSS_PLL_CONTROL); l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ dss_write_reg(DSS_PLL_CONTROL, l); }
int dss_init(void) { int r; u32 rev; dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } /* We need to wait here a bit, otherwise we sometimes start to get * synclost errors. I believe we could wait for one framedone or * perhaps vsync interrupt, but, because dispc is not initialized yet, * we don't have access to the irq register. */ msleep(400); _omap_dss_reset(); /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); #ifdef CONFIG_OMAP2_DSS_VENC REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); return 0; fail1: iounmap(dss.base); fail0: return r; }
void dss_sdi_init(int datapairs) { u32 l; BUG_ON(datapairs > 3 || datapairs < 1); l = dss_read_reg(DSS_SDI_CONTROL); l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ dss_write_reg(DSS_SDI_CONTROL, l); l = dss_read_reg(DSS_PLL_CONTROL); l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ dss_write_reg(DSS_PLL_CONTROL, l); /* Reset SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ udelay(1); /* wait 2x PCLK */ /* Lock SDI PLL */ REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ /* Waiting for PLL lock request to complete */ while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) ; /* Clearing PLL_GO bit */ REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); /* Waiting for PLL to lock */ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) ; dispc_lcd_enable_signal(1); /* Waiting for SDI reset to complete */ while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) ; }
void dss_select_clk_source(bool dsi, bool dispc) { u32 r; r = dss_read_reg(DSS_CONTROL); r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */ if (cpu_is_omap44xx()) r = FLD_MOD(r, dsi, 10, 10); /* DSI2_CLK_SWITCH */ r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */ /* TODO: extend for LCD2 and HDMI */ dss_write_reg(DSS_CONTROL, r); }
void dss_select_clk_source_dsi(enum dsi lcd_ix, bool dsi, bool lcd) { u32 r; r = dss_read_reg(DSS_CONTROL); if (lcd_ix == dsi1) { r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */ r = FLD_MOD(r, lcd, 0, 0); /* LCD1_CLK_SWITCH */ } else { r = FLD_MOD(r, dsi, 10, 10); /* DSI2_CLK_SWITCH */ r = FLD_MOD(r, lcd, 12, 12); /* LCD2_CLK_SWITCH */ } dss_write_reg(DSS_CONTROL, r); }
static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) { u32 irqstatus; irqstatus = dss_read_reg(DSS_IRQSTATUS); if (irqstatus & (1<<0)) /* DISPC_IRQ */ dispc_irq_handler(); #ifdef CONFIG_OMAP2_DSS_DSI if (irqstatus & (1<<1)) /* DSI_IRQ */ dsi_irq_handler(); #endif return IRQ_HANDLED; }
int dss_get_dispc_clk_source(void) { return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0); }
int dss_get_dsi_clk_source(void) { return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1); }
int dss_init(bool skip_init) { int r; u32 rev; dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } if (!skip_init) { /* disable LCD and DIGIT output. This seems to fix the synclost * problem that we get, if the bootloader starts the DSS and * the kernel resets it */ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); /* We need to wait here a bit, otherwise we sometimes start to * get synclost errors, and after that only power cycle will * restore DSS functionality. I have no idea why this happens. * And we have to wait _before_ resetting the DSS, but after * enabling clocks. */ msleep(50); _omap_dss_reset(); } /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); #ifdef CONFIG_OMAP2_DSS_VENC REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif #ifdef CONFIG_OMAP2_DSS_DSI /* disable the dsi interrupts so no spurious dsi irq's are deliverd * before the dsi block is fully initialzed -- this is especially an * issue if skip_init is true, as resetting the dss block would clear * these interupts anyway */ omap_writel(0, 0x4804FC1C); #endif r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); return 0; fail1: iounmap(dss.base); fail0: return r; }
int dss_get_dsi_clk_source_status(void) { return FLD_GET(dss_read_reg(DSS_SDI_STATUS), 1, 1); }
int dss_init(bool skip_init) { int r; u32 rev; dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } if (!skip_init) { /* disable LCD and DIGIT output. This seems to fix the synclost * problem that we get, if the bootloader starts the DSS and * the kernel resets it */ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); /* We need to wait here a bit, otherwise we sometimes start to * get synclost errors, and after that only power cycle will * restore DSS functionality. I have no idea why this happens. * And we have to wait _before_ resetting the DSS, but after * enabling clocks. */ msleep(50); _omap_dss_reset(); } /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); #ifdef CONFIG_OMAP2_DSS_VENC REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } if (cpu_is_omap34xx()) { dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); if (IS_ERR(dss.dpll4_m4_ck)) { DSSERR("Failed to get dpll4_m4_ck\n"); r = PTR_ERR(dss.dpll4_m4_ck); goto fail2; } } dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); return 0; fail2: free_irq(INT_24XX_DSS_IRQ, NULL); fail1: iounmap(dss.base); fail0: return r; }
int dss_get_dispc_clk_source_status(void) { return FLD_GET(dss_read_reg(DSS_SDI_STATUS), 0, 0); }
int dss_init(struct platform_device *pdev) { int r = 0, dss_irq; u32 rev; struct resource *dss_mem; bool skip_init = false; dss.pdata = pdev->dev.platform_data; dss.pdev = pdev; if (cpu_is_omap44xx()) dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); else dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!dss_mem) { WARN_ON(1); r = -ENODEV; goto fail0; } dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); if (!dss.base) { DSSERR("can't ioremap DSS\n"); r = -ENOMEM; goto fail0; } dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M | DSS_CLK_96M); dss_mainclk_enable(); #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT /* DISPC_CONTROL */ if (omap_readl(0x48050440) & 1) /* LCD enabled? */ skip_init = true; #endif if (!skip_init) { /* disable LCD and DIGIT output. This seems to fix the synclost * problem that we get, if the bootloader starts the DSS and * the kernel resets it */ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); /* We need to wait here a bit, otherwise we sometimes start to * get synclost errors, and after that only power cycle will * restore DSS functionality. I have no idea why this happens. * And we have to wait _before_ resetting the DSS, but after * enabling clocks. */ msleep(50); } /* autoidle */ REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); #ifdef CONFIG_OMAP2_DSS_VENC REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ #endif if (!cpu_is_omap44xx()) r = request_irq(INT_24XX_DSS_IRQ, cpu_is_omap24xx() ? dss_irq_handler_omap2 : dss_irq_handler_omap3, 0, "OMAP DSS", NULL); else { dss_irq = platform_get_irq(pdev, 0); r = request_irq(dss_irq, dss_irq_handler_omap2, 0, "OMAP DSS", NULL); } if (r < 0) { DSSERR("omap2 dss: request_irq failed\n"); goto fail1; } if (cpu_is_omap34xx()) { dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); if (IS_ERR(dss.dpll4_m4_ck)) { DSSERR("Failed to get dpll4_m4_ck\n"); r = PTR_ERR(dss.dpll4_m4_ck); goto fail2; } } dss.dsi1_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.dsi2_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.lcd1_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.lcd2_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; dss_save_context(); rev = dss_read_reg(DSS_REVISION); printk(KERN_INFO "OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M | DSS_CLK_96M); return 0; fail2: if (!cpu_is_omap44xx()) free_irq(INT_24XX_DSS_IRQ, NULL); fail1: iounmap(dss.base); fail0: return r; }