/* Worker function to compute each block's dominators */
static bool computeBlockDominators(CompilationUnit *cUnit, BasicBlock *bb) {
GrowableList *blockList = &cUnit->blockList;
int numTotalBlocks = blockList->numUsed;
BitVector *tempBlockV = cUnit->tempBlockV;
BitVectorIterator bvIterator;
/*
* The dominator of the entry block has been preset to itself and we need
* to skip the calculation here.
*/
if (bb == cUnit->entryBlock) return false;
dvmSetInitialBits(tempBlockV, numTotalBlocks);
/* Iterate through the predecessors */
dvmBitVectorIteratorInit(bb->predecessors, &bvIterator);
while (true) {
int predIdx = dvmBitVectorIteratorNext(&bvIterator);
if (predIdx == -1) break;
BasicBlock *predBB = (BasicBlock *) dvmGrowableListGetElement(
blockList, predIdx);
/* tempBlockV = tempBlockV ^ dominators */
dvmIntersectBitVectors(tempBlockV, tempBlockV, predBB->dominators);
}
dvmSetBit(tempBlockV, bb->id);
if (dvmCompareBitVectors(tempBlockV, bb->dominators)) {
dvmCopyBitVector(bb->dominators, tempBlockV);
return true;
}
return false;
}
/*
* Perform null-check on a register. sReg is the ssa register being checked,
* and mReg is the machine register holding the actual value. If internal state
* indicates that sReg has been checked before the check request is ignored.
*/
static ArmLIR *genNullCheck(CompilationUnit *cUnit, int sReg, int mReg,
int dOffset, ArmLIR *pcrLabel)
{
/* This particular Dalvik register has been null-checked */
if (dvmIsBitSet(cUnit->regPool->nullCheckedRegs, sReg)) {
return pcrLabel;
}
dvmSetBit(cUnit->regPool->nullCheckedRegs, sReg);
return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel);
}
/*
* Worker function to insert phi-operands with latest SSA names from
* predecessor blocks
*/
static bool insertPhiNodeOperands(CompilationUnit *cUnit, BasicBlock *bb) {
BitVector *ssaRegV = cUnit->tempSSARegisterV;
BitVectorIterator bvIterator;
GrowableList *blockList = &cUnit->blockList;
MIR *mir;
/* Phi nodes are at the beginning of each block */
for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
if (mir->dalvikInsn.opcode != (Opcode) kMirOpPhi)
return true;
int ssaReg = mir->ssaRep->defs[0];
int encodedDalvikValue =
(int) dvmGrowableListGetElement(cUnit->ssaToDalvikMap, ssaReg);
int dalvikReg = DECODE_REG(encodedDalvikValue);
dvmClearAllBits(ssaRegV);
/* Iterate through the predecessors */
dvmBitVectorIteratorInit(bb->predecessors, &bvIterator);
while (true) {
int predIdx = dvmBitVectorIteratorNext(&bvIterator);
if (predIdx == -1) break;
BasicBlock *predBB = (BasicBlock *) dvmGrowableListGetElement(
blockList, predIdx);
int encodedSSAValue =
predBB->dataFlowInfo->dalvikToSSAMap[dalvikReg];
int ssaReg = DECODE_REG(encodedSSAValue);
dvmSetBit(ssaRegV, ssaReg);
}
/* Count the number of SSA registers for a Dalvik register */
int numUses = dvmCountSetBits(ssaRegV);
mir->ssaRep->numUses = numUses;
mir->ssaRep->uses =
(int *) dvmCompilerNew(sizeof(int) * numUses, false);
mir->ssaRep->fpUse =
(bool *) dvmCompilerNew(sizeof(bool) * numUses, true);
BitVectorIterator phiIterator;
dvmBitVectorIteratorInit(ssaRegV, &phiIterator);
int *usePtr = mir->ssaRep->uses;
/* Set the uses array for the phi node */
while (true) {
int ssaRegIdx = dvmBitVectorIteratorNext(&phiIterator);
if (ssaRegIdx == -1) break;
*usePtr++ = ssaRegIdx;
}
}
return true;
}
static void checkForDominanceFrontier(BasicBlock *domBB,
const BasicBlock *succBB) {
/*
* TODO - evaluate whether phi will ever need to be inserted into exit
* blocks.
*/
if (succBB->iDom != domBB &&
succBB->blockType == kDalvikByteCode &&
succBB->hidden == false) {
dvmSetBit(domBB->domFrontier, succBB->id);
}
}
/* Compute dominators, immediate dominator, and dominance fronter */
static void computeDominators(CompilationUnit *cUnit) {
int numReachableBlocks = cUnit->numReachableBlocks;
int numTotalBlocks = cUnit->blockList.numUsed;
/* Initialize domination-related data structures */
dvmCompilerDataFlowAnalysisDispatcher(cUnit, initializeDominationInfo,
kReachableNodes,
false /* isIterative */);
/* Set the dominator for the root node */
dvmClearAllBits(cUnit->entryBlock->dominators);
dvmSetBit(cUnit->entryBlock->dominators, cUnit->entryBlock->id);
if (cUnit->tempBlockV == NULL) {
cUnit->tempBlockV = dvmCompilerAllocBitVector(numTotalBlocks,
false /* expandable */);
} else {
dvmClearAllBits(cUnit->tempBlockV);
}
dvmCompilerDataFlowAnalysisDispatcher(cUnit, computeBlockDominators,
kPreOrderDFSTraversal,
true /* isIterative */);
cUnit->entryBlock->iDom = NULL;
dvmCompilerDataFlowAnalysisDispatcher(cUnit, computeImmediateDominator,
kReachableNodes,
false /* isIterative */);
/*
* Now go ahead and compute the post order traversal based on the
* iDominated sets.
*/
if (cUnit->domPostOrderTraversal.elemList == NULL) {
dvmInitGrowableList(&cUnit->domPostOrderTraversal, numReachableBlocks);
} else {
cUnit->domPostOrderTraversal.numUsed = 0;
}
computeDomPostOrderTraversal(cUnit, cUnit->entryBlock);
assert(cUnit->domPostOrderTraversal.numUsed ==
(unsigned) cUnit->numReachableBlocks);
/* Now compute the dominance frontier for each block */
dvmCompilerDataFlowAnalysisDispatcher(cUnit, computeDominanceFrontier,
kPostOrderDOMTraversal,
false /* isIterative */);
}
/*
* Add a register pair to the LIVE set.
*/
static inline void GENW(BitVector* workBits, u4 regIndex)
{
dvmSetBit(workBits, regIndex);
dvmSetBit(workBits, regIndex+1);
}
