static void ls_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar; for (bar = BAR_0; bar <= BAR_5; bar++) dw_pcie_ep_reset_bar(pci, bar); }
static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar) { struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); u32 atu_index = ep->bar_to_atu[bar]; dw_pcie_ep_reset_bar(pci, bar); dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); clear_bit(atu_index, &ep->ib_window_map); }
int dw_pcie_ep_init(struct dw_pcie_ep *ep) { int ret; void *addr; enum pci_barno bar; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; struct device_node *np = dev->of_node; if (!pci->dbi_base || !pci->dbi_base2) { dev_err(dev, "dbi_base/deb_base2 is not populated\n"); return -EINVAL; } ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { dev_err(dev, "unable to read *num-ib-windows* property\n"); return ret; } ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); if (ret < 0) { dev_err(dev, "unable to read *num-ob-windows* property\n"); return ret; } addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows, GFP_KERNEL); if (!addr) return -ENOMEM; ep->outbound_addr = addr; for (bar = BAR_0; bar <= BAR_5; bar++) dw_pcie_ep_reset_bar(pci, bar); if (ep->ops->ep_init) ep->ops->ep_init(ep); epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "failed to create epc device\n"); return PTR_ERR(epc); } ret = of_property_read_u8(np, "max-functions", &epc->max_functions); if (ret < 0) epc->max_functions = 1; ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size); if (ret < 0) { dev_err(dev, "Failed to initialize address space\n"); return ret; } ep->epc = epc; epc_set_drvdata(epc, ep); dw_pcie_setup(pci); return 0; }