int main(void)
{
mailbox = (unsigned *)0x00006000;
mailbox1 = (unsigned *)0x00006100;
// Initialize the mailbox
mailbox[0] = 0x00000000;
mailbox1[0] = 0x00000000;
// Preparing for the interrupt
// Attach the ISR with this interrupt
e_irq_attach(E_MESSAGE_INT, int_isr);
// Clear the IMASK
e_irq_mask(E_MESSAGE_INT, E_FALSE);
// Enable the global interrupt
e_irq_global_mask(E_FALSE);
// Making slave_core into idle and wait for the finishing transfer interrupt
__asm__ __volatile__("idle");
// Showing coming back from the interrupt
mailbox1[0] = 0xffffffff;
// Set the IMASK
e_irq_mask(E_MESSAGE_INT, E_TRUE);
// Disable the global interrupt
e_irq_global_mask(E_TRUE);
return 0;
}
int main(void)
{
unsigned i;
*signal = start;
//attach the isr handlers
e_irq_attach(E_SW_EXCEPTION, swexception_isr);
e_irq_attach(E_MEM_FAULT, memfault_isr);
e_irq_attach(E_TIMER0_INT, timer0_isr);
e_irq_attach(E_TIMER1_INT, timer1_isr);
e_irq_attach(E_DMA0_INT, dma0_isr);
e_irq_attach(E_DMA1_INT, dma1_isr);
e_irq_attach(E_USER_INT, user_isr);
//enable interrupts
e_irq_global_mask(E_FALSE);
e_reg_write(E_REG_IMASK,0x0);
//initialize the target mem
result = (unsigned *)resultbase;
for(i=0;i<7;i++)
{
result[i] = 0x0;
}
//wait for the finished signal from master
while(*signal != finish) ;
return EXIT_SUCCESS;
}
int main(void) {
int i;
int *pt;
e_irq_attach(E_SW_EXCEPTION, swexception_isr);
e_irq_attach(E_MEM_FAULT, memfault_isr);
e_irq_attach(E_TIMER0_INT, timer0_isr);
e_irq_attach(E_TIMER1_INT, timer1_isr);
e_irq_attach(E_DMA0_INT, dma0_isr);
e_irq_attach(E_DMA1_INT, dma1_isr);
e_irq_attach(E_USER_INT, user_isr);
e_irq_global_mask(E_FALSE);
e_reg_write(E_REG_IMASK,0x0);
//reset the target mem
pt = (int *)0x5200;
for(i=0;i<7;i++)
{
pt[i] = 0x0;
}
while(1) ;
return EXIT_SUCCESS;
}
int main(int argc, char** args) {
(void) argc; (void) args;
e_irq_global_mask(E_TRUE);
const u32 w = *(u32*) 0x40;
const u32 h = *(u32*) 0x44;
f32* b_kh = b;
f32* c_jh;
// if (a != (const f32*) 0x2000 || b != (const f32*) 0x4000 || c != (const f32*) 0x6000) {
// *(UserInterrupt*) 0x24 = UserInterrupt::Error;
// return 0;
// }
e_ctimer_set(E_CTIMER_0, E_CTIMER_MAX);
e_ctimer_set(E_CTIMER_1, E_CTIMER_MAX);
e_ctimer_start(E_CTIMER_0, E_CTIMER_FPU_INST);
e_ctimer_start(E_CTIMER_1, E_CTIMER_CLK);
for (u32 k = 0; k < w; k += 1) {
c_jh = c;
for (u32 j = 0; j < h; j += 1) {
f32 a_jw_k = a[j*w + k];
for (u32 i = 0; i < h;) {
if (i + 1 < h) {
c_jh[i ] += a_jw_k * b_kh[i ];
c_jh[i + 1] += a_jw_k * b_kh[i + 1];
i += 2;
} else {
c_jh[i ] += a_jw_k * b_kh[i ];
i += 1;
}
}
c_jh += h;
}
b_kh += h;
}
// for (u32 k = 0; k < w; k += 1) { // this order of loops is faster than the others on epiphany
// for (u32 j = 0; j < h; j += 1) {
// for (u32 i = 0; i < h; i += 1) {
// c[j*h + i] += a[j*w + k] * b[k*h + i];
// }
// }
// }
u32 cycles = (u32) e_ctimer_get(E_CTIMER_1);
u32 fpops = (u32) e_ctimer_get(E_CTIMER_0);
*(u32*) 0x48 = E_CTIMER_MAX - cycles;
*(u32*) 0x4c = E_CTIMER_MAX - fpops;
*(UserInterrupt*) 0x24 = UserInterrupt::Done;
return 0;
}
int trace_start_wait_all()
{
unsigned irqState;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_trace_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
__asm__ __volatile__("wand"); // Set our WAND bit
__asm__ __volatile__("idle"); // Idle and wait for an interrupt
irqState = e_reg_read(E_REG_STATUS);
irqState = irqState & (~0x8); // This is the WAND interrupt flag
e_reg_write(E_REG_FSTATUS, irqState);
//e_ctimer_start(E_CTIMER_1, E_CTIMER_CLK); // Start counting
return 0;
}
/**
* Initialize data structures, call this first before using trace functions
*/
int trace_init()
{
// If I am the master
if(e_get_coreid() == TRACE_MASTER_ID) {
// setup my DMA engine
setupDMA2(); // REMEMBER TO CHANGE
}
//register timer ISR
e_irq_global_mask(0);
e_irq_attach(E_TIMER1_INT, timer1_trace_isr);
e_irq_mask(E_TIMER1_INT, 0);
// setup timer 1 for work
e_ctimer_stop(E_CTIMER_1);
e_ctimer_set(E_CTIMER_1, E_CTIMER_MAX);
logCoreid = (e_get_coreid()& 0xFFF) << 8; // make it easy to use core-id
return 0;
}
int main(void) {
//initialize
int i;
unsigned row, col, delay, num;
unsigned *ivt;
e_irq_global_mask(E_FALSE);
e_irq_attach(E_WAND_INT, wand_isr);
e_irq_mask(E_WAND_INT, E_FALSE);
row = e_group_config.core_row;
col = e_group_config.core_col;
num = row * e_group_config.group_cols + col;
pause = (volatile uint32_t *) (0x7000);
result = (volatile unsigned *) (0x8f000000 + 0x4*num);
delay = 0x2000 * num + 0x2000;
if (num == 0)
*pause = 0;
*result = 0xdeadbeef;
for(i=0; i<0x10000; i++)
{
*result = i;
e_wait(E_CTIMER_0, delay);
if (num == 0)
while ((*pause));
__asm__ __volatile__("wand");
__asm__ __volatile__("idle");
// clear wand bit
state = e_reg_read(E_REG_STATUS);
state = state & (~0x8);
e_reg_write(E_REG_FSTATUS, state);
}
return EXIT_SUCCESS;
}
int main(void)
{
unsigned *a, *b, *c, *size;
unsigned i, j;
int coreid;
unsigned *src, *dest;
unsigned row, col;
coreid = e_get_coreid() ^ 0x0c3; // Copy to the opposite core in chip
src = (unsigned *) 0x6000;
dest = (void *) ((coreid<<20) | 0x6000);
size = (unsigned *) 0x1e00;
a = (unsigned *) 0x2000;
b = (unsigned *) 0x4000;
c = (unsigned *) 0x6000;
// Doing convolution to generate busy level
for (i=0; i<(*size); i++)
{
for (j=0; j<=i; j++)
{
c[i] += a[i-j] * b[j];
}
}
for(i=0; i<100000; i++)
{
e_dma_copy(dest, src, *size);
}
// clear the IMASK
e_irq_mask(E_SYNC, E_FALSE);
// enable the global interrupt
e_irq_global_mask(E_FALSE);
__asm__ __volatile__("idle");
return EXIT_SUCCESS;
}
int main(void)
{
e_coreid_t coreid;
unsigned int *po;
unsigned int reg;
unsigned int p_value;
unsigned int flag3, flag4, flag5;
unsigned int temp;
unsigned int k;
unsigned *pass;
pass = (unsigned *)7000;
po= (unsigned *) 0x600c;
po[0] = 0x00000000;
global_index = (unsigned *)0x80802000;
while(1)
{
pass[0] = (unsigned)0x00000000;
while(po[0] == (unsigned) 0x00000000)
{};
sprintf(outbuf,"");
// Store the previous value of the register
p_value = e_reg_read(*po);
// Disable interrupts
e_irq_global_mask(E_TRUE);
//For register EILAT
// Clear the EILAT
e_reg_write(E_REG_ILATCL, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x00000000)
{
flag3=1;
}
else
{
flag3=0;
sprintf(outbuf,"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x00000000);
global_index[0] = global_index[0] + 1;
}
// Set the EILAT
e_reg_write(E_REG_ILATST, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x000003ff)
{
flag4=1;
}else
{
flag4=0;
sprintf(outbuf + strlen(outbuf),"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x000003ff);
global_index[0] = global_index[0] + 1;
}
// Clear the EILAT
e_reg_write(E_REG_ILATCL, (unsigned)0xffffffff);
temp = e_reg_read(*po);
if (temp == (unsigned)0x00000000)
{
flag5=1;
}else{
flag5=0;
sprintf(outbuf + strlen(outbuf),"We get 0x%08x instead of 0x%08x, ILAT\n", temp, 0x00000000);
global_index[0] = global_index[0] + 1;
}
if ((flag3 == 1) && (flag4 == 1) && (flag5 == 1))
{
pass[0] = 0xdeadbeef;
}
// Set the register to the previous value
e_reg_write(*po, p_value);
po[0] = (unsigned) 0x00000000;
// Enable the interrupts
e_irq_global_mask(E_FALSE);
}
return EXIT_SUCCESS;
}
