void __init pplus_set_VIA_IDE_legacy(void)
{
unsigned short vend, dev;
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put back original "standard" port base addresses */
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_0, 0x1f1);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_1, 0x3f5);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_2, 0x171);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_3, 0x375);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_4, 0xcc01);
/* put into legacy mode */
early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
&temp);
temp &= ~0x05;
early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
temp);
}
}
void pplus_set_VIA_IDE_native(void)
{
unsigned short vend, dev;
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put into native mode */
early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
&temp);
temp |= 0x05;
early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
temp);
}
}
static int __init tx4927_pcibios_init(void)
{
unsigned int id;
u32 pci_devfn;
int devfn_start = 0;
int devfn_stop = 0xff;
int busno = 0; /* One bus on the Toshiba */
struct pci_controller *hose = &tx4927_controller;
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
"-\n");
for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
early_read_config_dword(hose, busno, busno, pci_devfn,
PCI_VENDOR_ID, &id);
if (id == 0xffffffff) {
continue;
}
if (id == 0x94601055) {
u8 v08_64;
u32 v32_b0;
u8 v08_e1;
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
char *s = " sb/isa --";
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
s);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x64, &v08_64);
early_read_config_dword(hose, busno, busno,
pci_devfn, 0xb0, &v32_b0);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0xe1, &v08_e1);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
/* serial irq control */
v08_64 = 0xd0;
/* serial irq pin */
v32_b0 |= 0x00010000;
/* ide irq on isa14 */
v08_e1 &= 0xf0;
v08_e1 |= 0x0d;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x64, v08_64);
early_write_config_dword(hose, busno, busno,
pci_devfn, 0xb0, v32_b0);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0xe1, v08_e1);
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
{
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x64,
&v08_64);
early_read_config_dword(hose, busno, busno,
pci_devfn, 0xb0,
&v32_b0);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0xe1,
&v08_e1);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x64 = 0x%02x\n", s, v08_64);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0xb0 = 0x%02x\n", s, v32_b0);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0xe1 = 0x%02x\n", s, v08_e1);
}
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
s);
}
if (id == 0x91301055) {
u8 v08_04;
u8 v08_09;
u8 v08_41;
u8 v08_43;
u8 v08_5c;
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
char *s = " sb/ide --";
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
s);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x04, &v08_04);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x09, &v08_09);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x41, &v08_41);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x43, &v08_43);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x5c, &v08_5c);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s beg 0x5c = 0x%02x\n", s, v08_5c);
/* enable ide master/io */
v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
/* enable ide native mode */
v08_09 |= 0x05;
/* enable primary ide */
v08_41 |= 0x80;
/* enable secondary ide */
v08_43 |= 0x80;
/*
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
*
* This line of code is intended to provide the user with a work
* around solution to the anomalies cited in SMSC's anomaly sheet
* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
*
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
*/
v08_5c |= 0x01;
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s mid 0x5c = 0x%02x\n", s, v08_5c);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x5c, v08_5c);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x04, v08_04);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x09, v08_09);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x41, v08_41);
early_write_config_byte(hose, busno, busno,
pci_devfn, 0x43, v08_43);
#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
{
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x04,
&v08_04);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x09,
&v08_09);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x41,
&v08_41);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x43,
&v08_43);
early_read_config_byte(hose, busno, busno,
pci_devfn, 0x5c,
&v08_5c);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x04 = 0x%02x\n", s, v08_04);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x09 = 0x%02x\n", s, v08_09);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x41 = 0x%02x\n", s, v08_41);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x43 = 0x%02x\n", s, v08_43);
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
":%s end 0x5c = 0x%02x\n", s, v08_5c);
}
#endif
TOSHIBA_RBTX4927_SETUP_DPRINTK
(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
s);
}
}
register_pci_controller(&tx4927_controller);
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
"+\n");
return 0;
}
