/* Early setup - runs on TP1 after cache probe */
static void brcmstb_init_secondary(void)
{
#if defined(CONFIG_BMIPS4380)
unsigned long cbr = BMIPS_GET_CBR();
unsigned long old_vec = DEV_RD(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
/* make sure the NMI vector is in kseg0 now that we've booted */
DEV_WR_RB(cbr + BMIPS_RELO_VECTOR_CONTROL_1, old_vec & ~0x20000000);
#endif
brcmstb_ack_ipi(0);
write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
irq_enable_hazard();
early_tlb_init();
}
void __init
prom_init(void)
{
unsigned long extmem = 0, off, data;
static unsigned long mem;
unsigned long off1, data1;
struct nvram_header *header;
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
/* These are not really being used anywhere - LR */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
#endif
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
off1 = off + 4;
data1 = *(unsigned long *)off1;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if ((*(unsigned long *)(off + mem) == data) &&
(*(unsigned long *)(off1 + mem) == data1))
break;
}
detectmem = mem;
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
/* CFE could have loaded nvram during netboot
* to top 32KB of RAM, Just check for nvram signature
* and copy it to nvram space embedded in linux
* image for later use by nvram driver.
*/
header = (struct nvram_header *)(KSEG0ADDR(mem - NVRAM_SPACE));
if (ltoh32(header->magic) == NVRAM_MAGIC) {
uint32 *src = (uint32 *)header;
uint32 *dst = (uint32 *)ram_nvram_buf;
uint32 i;
printk("Copying NVRAM bytes: %d from: 0x%p To: 0x%p\n", ltoh32(header->len),
src, dst);
for (i = 0; i < ltoh32(header->len) && i < NVRAM_SPACE; i += 4)
*dst++ = ltoh32(*src++);
}
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
void __init
prom_init(void)
{
unsigned long mem, extmem = 0, off, data;
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if (*(unsigned long *)(off + mem) == data)
break;
}
#if CONFIG_RAM_SIZE
{
unsigned long config_mem;
config_mem = CONFIG_RAM_SIZE * 0x100000;
if (config_mem < mem)
mem = config_mem;
}
#endif
#ifdef CONFIG_HIGHMEM
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#ifdef CONFIG_HIGHMEM
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}