static u8 mainboard_smi_ec(void)
{
u8 src;
#if CONFIG(ELOG_GSMI)
static int battery_critical_logged;
#endif
ec_kbc_write_cmd(0x56);
src = ec_kbc_read_ob();
printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src);
switch (src) {
case EC_BATTERY_CRITICAL:
#if CONFIG(ELOG_GSMI)
if (!battery_critical_logged)
elog_add_event_byte(ELOG_TYPE_EC_EVENT,
EC_EVENT_BATTERY_CRITICAL);
battery_critical_logged = 1;
#endif
break;
case EC_LID_CLOSE:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10));
break;
}
return src;
}
static void pch_log_wake_source(struct chipset_power_state *ps)
{
/* Power Button */
if (ps->pm1_sts & PWRBTN_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
/* RTC */
if (ps->pm1_sts & RTC_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
/* PCI Express (TODO: determine wake device) */
if (ps->pm1_sts & PCIEXPWAK_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
/* PME */
if(ps->gpe0_sts[GPE0_A] & CSE_PME_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
/* SMBUS Wake */
if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
/* ACPI Wake Event - Always Log prev_sleep_state*/
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
/* Log GPIO events in set A-D */
pch_log_gpio_gpe(ps->gpe0_sts[GPE0_A], ps->gpe0_en[GPE0_A], 0);
pch_log_gpio_gpe(ps->gpe0_sts[GPE0_B], ps->gpe0_en[GPE0_B], 32);
pch_log_gpio_gpe(ps->gpe0_sts[GPE0_C], ps->gpe0_en[GPE0_C], 64);
pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96);
}
static void elog_add_boot_reason(void *unused)
{
int rec = vboot_recovery_mode_enabled();
int dev = vboot_developer_mode_enabled();
if (!rec && !dev)
return;
if (rec) {
u8 reason = vboot_check_recovery_request();
elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE, reason);
printk(BIOS_DEBUG, "%s: Logged recovery mode boot%s, "
"reason: 0x%02x\n", __func__,
dev ? " (Dev-switch on)" : "", reason);
}
if (dev) {
int log_event = 1;
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
/* Skip logging developer mode in ACPI resume path */
if (acpi_is_wakeup())
log_event = 0;
#endif
if (log_event) {
elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE);
printk(BIOS_DEBUG, "%s: Logged dev mode boot\n",
__func__);
}
}
}
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
return cmd;
}
void elog_add_boot_reason(void)
{
if (developer_mode_enabled()) {
elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE);
printk(BIOS_DEBUG, "%s: Logged dev mode boot\n", __func__);
} else if (recovery_mode_enabled()) {
u8 reason = 0;
#if CONFIG_VBOOT_VERIFY_FIRMWARE
struct vboot_handoff *vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
reason = get_recovery_mode_from_vbnv();
if (vbho && !reason) {
VbSharedDataHeader *sd = (VbSharedDataHeader *)
vbho->shared_data;
reason = sd->recovery_reason;
}
#endif
elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE,
reason ? reason : ELOG_CROS_RECOVERY_MODE_BUTTON);
printk(BIOS_DEBUG, "%s: Logged recovery mode boot, "
"reason: 0x%02x\n", __func__, reason);
} else {
printk(BIOS_DEBUG, "%s: Normal mode boot, nothing "
"interesting to log\n", __func__);
}
}
void google_chromeec_log_events(uint64_t mask)
{
u8 event;
uint64_t wake_mask;
bool restore_wake_mask = false;
if (!IS_ENABLED(CONFIG_ELOG))
return;
/*
* If the EC supports unified wake masks, then there is no need to set
* wake mask before reading out the host events.
*/
if (google_chromeec_check_feature(EC_FEATURE_UNIFIED_WAKE_MASKS) != 1) {
wake_mask = google_chromeec_get_wake_mask();
google_chromeec_set_wake_mask(mask);
restore_wake_mask = true;
}
while ((event = google_chromeec_get_event()) != 0) {
if (EC_HOST_EVENT_MASK(event) & mask)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
}
if (restore_wake_mask)
google_chromeec_set_wake_mask(wake_mask);
}
static void ene_kb3940q_log_events(void)
{
#if CONFIG(ELOG)
u8 reason = ec_mem_read(EC_SHUTDOWN_REASON);
if (reason)
elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason);
#endif
}
static void pch_log_power_and_resets(struct chipset_power_state *ps)
{
/* Thermal Trip Status */
if (ps->gen_pmcon2 & THERMTRIP_STS)
elog_add_event(ELOG_TYPE_THERM_TRIP);
/* PWR_FLR Power Failure */
if (ps->gen_pmcon2 & PWROK_FLR)
elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */
if (ps->gen_pmcon3 & SUS_PWR_FLR)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* SYS_PWROK Failure */
if (ps->gen_pmcon2 & SYSPWR_FLR)
elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
/* PWROK Failure */
if (ps->gen_pmcon2 & PWROK_FLR)
elog_add_event(ELOG_TYPE_PWROK_FAIL);
/* TCO Timeout */
if (ps->prev_sleep_state != 3 &&
ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
if (ps->pm1_sts & PRBTNOR_STS)
elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
/* RTC reset */
if (ps->gen_pmcon3 & RTC_BATTERY_DEAD)
elog_add_event(ELOG_TYPE_RTC_RESET);
/* System Reset Status (reset button pushed) */
if (ps->gen_pmcon2 & SYSTEM_RESET_STS)
elog_add_event(ELOG_TYPE_RESET_BUTTON);
/* General Reset Status */
if (ps->gen_pmcon3 & GEN_RST_STS)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */
if (ps->prev_sleep_state != SLEEP_STATE_S0)
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
}
static void google_chromeec_elog_add_recovery_event(void *unused)
{
uint64_t *events = cbmem_find(CBMEM_ID_EC_HOSTEVENT);
uint8_t event_byte = EC_EVENT_KEYBOARD_RECOVERY;
if (!events)
return;
if (!(*events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
return;
if (*events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))
event_byte = EC_EVENT_KEYBOARD_RECOVERY_HWREINIT;
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte);
}
void mainboard_smi_gpi(u32 gpi_sts)
{
printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts);
if (gpi_sts & (1 << EC_SMI_GPI)) {
/* Process all pending events from EC */
while (mainboard_smi_ec() != EC_NO_EVENT);
}
else if (gpi_sts & (1 << EC_LID_GPI)) {
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10));
}
}
static int chromeec_process_one_event(void)
{
uint8_t event = google_chromeec_get_event();
/* Log this event */
if (IS_ENABLED(CONFIG_ELOG_GSMI) && event)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
switch (event) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
poweroff();
break;
}
return !!event;
}
void google_chromeec_log_events(u32 mask)
{
#if CONFIG_ELOG
u8 event;
u32 wake_mask;
/* Set wake mask so events will be read from ACPI interface */
wake_mask = google_chromeec_get_wake_mask();
google_chromeec_set_wake_mask(mask);
while ((event = google_chromeec_get_event()) != 0) {
if (EC_HOST_EVENT_MASK(event) & mask)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
}
google_chromeec_set_wake_mask(wake_mask);
#endif
}
static void log_wake_events(const struct chipset_power_state *ps)
{
const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS |
PCIE_WAKE2_STS | PCIE_WAKE1_STS |
PCIE_WAKE0_STS;
uint32_t gpe0_sts;
uint32_t gpio_mask;
int i;
/* Mask off disabled events. */
gpe0_sts = ps->gpe0_sts & ps->gpe0_en;
if (ps->pm1_sts & WAK_STS) {
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
acpi_slp_type == 3 ? 3 : 5);
}
if (ps->pm1_sts & PWRBTN_STS) {
elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
}
if (ps->pm1_sts & RTC_STS) {
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
}
if (gpe0_sts & PME_B0_EN) {
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
}
if (gpe0_sts & pcie_wake_mask) {
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
}
gpio_mask = SUS_GPIO_STS0;
i = 0;
while (gpio_mask) {
if (gpio_mask & gpe0_sts) {
elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
}
gpio_mask <<= 1;
i++;
}
}
static void google_chromeec_log_device_events(uint64_t mask)
{
uint64_t events;
int i;
if (!IS_ENABLED(CONFIG_ELOG) || !mask)
return;
if (google_chromeec_check_feature(EC_FEATURE_DEVICE_EVENT) != 1)
return;
events = google_chromeec_get_device_current_events() & mask;
printk(BIOS_INFO, "EC Device Events: 0x%016llx\n", events);
for (i = 0; i < sizeof(events) * 8; i++) {
if (EC_DEVICE_EVENT_MASK(i) & events)
elog_add_event_byte(ELOG_TYPE_EC_DEVICE_EVENT, i);
}
}
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | (0xf << 10));
break;
}
return cmd;
}
/* Find the last port80 code from the previous boot */
static u16 google_chromeec_get_port80_last_boot(void)
{
struct ec_response_port80_last_boot rsp;
struct chromeec_command cmd = {
.cmd_code = EC_CMD_PORT80_LAST_BOOT,
.cmd_data_out = &rsp,
.cmd_size_out = sizeof(rsp),
};
/* Get last port80 code */
if (google_chromeec_command(&cmd) == 0)
return rsp.code;
return 0;
}
#endif
void google_chromeec_log_events(u32 mask)
{
#if CONFIG_ELOG
u8 event;
u16 code;
/* Find the last port80 code */
code = google_chromeec_get_port80_last_boot();
/* Log the last post code only if it is abornmal */
if (code > 0 && code != POST_OS_BOOT && code != POST_OS_RESUME)
printk(BIOS_DEBUG, "Chrome EC: Last POST code was 0x%02x\n",
code);
while ((event = google_chromeec_get_event()) != 0) {
if (EC_HOST_EVENT_MASK(event) & mask)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
}
#endif
}
static u8 mainboard_smi_ec(void)
{
u8 cmd = 0;
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
u32 pm1_cnt;
cmd = google_chromeec_get_event();
/* Log this event */
if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
break;
}
#endif
return cmd;
}
static u8 mainboard_smi_ec(void)
{
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
#endif
switch (cmd) {
case EC_HOST_EVENT_LID_CLOSED:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
/* Go to S5 */
pm1_cnt = inl(get_pmbase() + PM1_CNT);
pm1_cnt |= (0xf << 10);
outl(pm1_cnt, get_pmbase() + PM1_CNT);
break;
}
return cmd;
}
void pch_log_state(void)
{
u16 pm1_sts, gen_pmcon_3, tco2_sts;
u8 gen_pmcon_2;
struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
if (!lpc)
return;
pm1_sts = inw(get_pmbase() + PM1_STS);
tco2_sts = inw(get_pmbase() + TCO2_STS);
gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
/* PWR_FLR Power Failure */
if (gen_pmcon_2 & (1 << 0))
elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */
if (gen_pmcon_3 & (1 << 14))
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* SYS_PWROK Failure */
if (gen_pmcon_2 & (1 << 1))
elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
/* PWROK Failure */
if (gen_pmcon_2 & (1 << 0))
elog_add_event(ELOG_TYPE_PWROK_FAIL);
/* Second TCO Timeout */
if (tco2_sts & (1 << 1))
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
if (pm1_sts & (1 << 11))
elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
/* System Reset Status (reset button pushed) */
if (gen_pmcon_2 & (1 << 4))
elog_add_event(ELOG_TYPE_RESET_BUTTON);
/* General Reset Status */
if (gen_pmcon_3 & (1 << 9))
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
*/
/* Power Button */
if (pm1_sts & (1 << 8))
elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
/* RTC */
if (pm1_sts & (1 << 10))
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
/* PCI Express (TODO: determine wake device) */
if (pm1_sts & (1 << 14))
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
/* GPE */
if (pch_is_lp())
pch_lp_log_gpe();
else
pch_log_gpe();
}
void pch_log_state(void)
{
u16 pm1_sts, gen_pmcon_3, tco2_sts;
u32 gpe0_sts, gpe0_en;
u8 gen_pmcon_2;
int i;
struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
if (!lpc)
return;
pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS);
gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN);
tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS);
gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
/* PWR_FLR Power Failure */
if (gen_pmcon_2 & (1 << 0))
elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */
if (gen_pmcon_3 & (1 << 14))
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* SYS_PWROK Failure */
if (gen_pmcon_2 & (1 << 1))
elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
/* PWROK Failure */
if (gen_pmcon_2 & (1 << 0))
elog_add_event(ELOG_TYPE_PWROK_FAIL);
/* Second TCO Timeout */
if (tco2_sts & (1 << 1))
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
if (pm1_sts & (1 << 11))
elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
/* System Reset Status (reset button pushed) */
if (gen_pmcon_2 & (1 << 4))
elog_add_event(ELOG_TYPE_RESET_BUTTON);
/* General Reset Status */
if (gen_pmcon_3 & (1 << 9))
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
*/
/* RTC */
if (pm1_sts & (1 << 10))
elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
/* PCI Express (TODO: determine wake device) */
if (pm1_sts & (1 << 14))
elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
/* PME (TODO: determine wake device) */
if (gpe0_sts & (1 << 13))
elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
/* Internal PME (TODO: determine wake device) */
if (gpe0_sts & (1 << 13))
elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
/* GPIO 0-15 */
for (i = 0; i < 16; i++) {
if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i))))
elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
}
/* SMBUS Wake */
if (gpe0_sts & (1 << 7))
elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
}