void SERCOM::setDataOrderSPI(SercomDataOrder dataOrder) { //Register enable-protected disableSPI(); sercom->SPI.CTRLA.bit.DORD = dataOrder; enableSPI(); }
void SERCOM::setBaudrateSPI(uint8_t divider) { //Can't divide by 0 if(divider == 0) return; //Register enable-protected disableSPI(); sercom->SPI.BAUD.reg = calculateBaudrateSynchronous( SERCOM_FREQ_REF / divider ); enableSPI(); }
void setup(void) { // Turn off interrupts cli(); // Reset buffer locations LightBuffer.bufferLocation = 0; SoundBuffer.bufferLocation = 0; setupIO(); prepareADC(); enableSPI(); setupTimer(); // Unleash the interrupts! sei(); }
void SERCOM::setClockModeSPI(SercomSpiClockMode clockMode) { int cpha, cpol; if((clockMode & (0x1ul)) == 0) cpha = 0; else cpha = 1; if((clockMode & (0x2ul)) == 0) cpol = 0; else cpol = 1; //Register enable-protected disableSPI(); sercom->SPI.CTRLA.bit.CPOL = cpol; sercom->SPI.CTRLA.bit.CPHA = cpha; enableSPI(); }
void enableExt(int nId, int nEXId, int nTigger, int nMask) { enableSPI(nId); //set GPX3_2 interrupt function #define GPXCON 0x11000C00 //GPX3CON |= 0xf << 8; *(volatile unsigned int*)(GPXCON + ((nEXId/8) << 5)) &= ~(0xf << ((nEXId%8) << 2)); *(volatile unsigned int*)(GPXCON + ((nEXId/8) << 5)) |= (0xf << ((nEXId%8) << 2)); //set trigger *(volatile unsigned int*)(EXT_INT_BASE + ((nEXId/8)<<2)) &= ~(0xf << ((nEXId%8) << 2)); *(volatile unsigned int*)(EXT_INT_BASE + ((nEXId/8)<<2)) |= (nTigger << ((nEXId%8) << 2)); //set filter *(volatile unsigned int*)(EXT_INT_BASE + 0x80 + ((nEXId/4)<<2)) |= (0xff << ((nEXId%4) << 3)); //set mask *(volatile unsigned int*)(EXT_INT_BASE + 0x100 + ((nEXId/8)<<2)) &= ~(1 << (nEXId%8)); }
int main(void) { /*******************GPIO configuration********************/ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA,DISABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB,ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB,DISABLE); /*****Master Mode*****/ GPIO_conf(GPIOA,GPIO_Pin_4,GPIO_Speed_50MHz,GPIO_Mode_AF_PP); //SPI1_NSS GPIO_conf(GPIOA,GPIO_Pin_5,GPIO_Speed_50MHz,GPIO_Mode_AF_PP); //SPI1_SCK GPIO_conf(GPIOA,GPIO_Pin_6,Input_Mode,GPIO_Mode_IPU); //SPI1_MISO GPIO_conf(GPIOA,GPIO_Pin_7,GPIO_Speed_50MHz,GPIO_Mode_AF_PP); //SPI1_MOSI /*****Slave Mode******/ GPIO_conf(GPIOB,GPIO_Pin_12,Input_Mode,GPIO_Mode_IN_FLOATING); //SPI3_NSS GPIO_conf(GPIOB,GPIO_Pin_13,Input_Mode,GPIO_Mode_IN_FLOATING); //SPI3_SCK GPIO_conf(GPIOB,GPIO_Pin_14,GPIO_Speed_50MHz,GPIO_Mode_AF_PP); //SPI3_MISO GPIO_conf(GPIOB,GPIO_Pin_15,Input_Mode,GPIO_Mode_IN_FLOATING); //SPI3_MOSI //uint32_t checkGPIOA_CRH = GPIOA->CRH; //uint32_t checkGPIOA_CRL = GPIOA->CRL; //uint32_t checkGPIOB_CRL = GPIOB->CRL; /*******************SPI configuration********************/ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1,ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1,DISABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2,ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2,DISABLE); SPI_conf(SPI1,SPI_Mode_Master,SPI_DataSize_8b,SPI_BaudRatePrescaler_4,SPI_FirstBit_LSB,idle0_1Edge); SPI_conf(SPI2,SPI_Mode_Slave,SPI_DataSize_8b,SPI_BaudRatePrescaler_2,SPI_FirstBit_LSB,idle0_1Edge); SPI_SSOutputCmd(SPI1,ENABLE); enableSPI(SPI1,ENABLE); enableSPI(SPI2,ENABLE); // uint32_t checkSPI1_CR1 = SPI1->CR1; // uint32_t checkSPI1_CR2 = SPI1->CR2; // uint32_t checkSPI1_CRCPR = SPI1->CRCPR; //uint32_t checkSPI2_CR1 = SPI2->CR1; //uint32_t checkSPI2_CR2 = SPI2->CR2; //uint32_t checkSPI2_CRCPR = SPI2->CRCPR; //rxOnlyMode(SPI1,ENABLE); //If Slave Transmitted and Master Received, Rx only mode should enabled after SPE = 1. uint16_t data1; uint16_t data2; while(1) { /*****Master Transmitted and Slave Received*****/ if( SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_TXE) ){ SPI_I2S_SendData(SPI1,'H'); } if( SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_RXNE) ){ data1 = SPI_I2S_ReceiveData(SPI2); } /*****Slave Transmitted and Master Received*****/ // if( SPI_I2S_GetFlagStatus(SPI2,SPI_I2S_FLAG_TXE) ){ // SPI_I2S_SendData(SPI2,'L'); // } // if( SPI_I2S_GetFlagStatus(SPI1,SPI_I2S_FLAG_RXNE) ){ // data2 = SPI_I2S_ReceiveData(SPI1); // } } }