/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only initializes the mmu in a quick and dirty way. * The memory that is used by BL2U is only mapped. ******************************************************************************/ void arm_bl2u_plat_arch_setup(void) { #if USE_COHERENT_MEM /* Ensure ARM platforms dont use coherent memory in BL2U */ assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif const mmap_region_t bl_regions[] = { MAP_BL2U_TOTAL, ARM_MAP_BL_RO, #if USE_ROMLIB ARM_MAP_ROMLIB_CODE, ARM_MAP_ROMLIB_DATA, #endif {0} }; setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_svc_mon(0); #else enable_mmu_el1(0); #endif arm_setup_romlib(); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. ******************************************************************************/ void bl2_plat_arch_setup(void) { rpi3_setup_page_tables(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END #if USE_COHERENT_MEM , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif ); enable_mmu_el1(0); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { ls_setup_page_tables(BL32_BASE, (BL32_END - BL32_BASE), BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END #if USE_COHERENT_MEM , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif ); enable_mmu_el1(0); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { const mmap_region_t bl_regions[] = { MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE, MT_MEMORY | MT_RW | MT_SECURE), MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_SECURE), MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_SECURE), MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE), {0} }; setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); }
/******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only initializes the mmu in a quick and dirty way. ******************************************************************************/ void ls_bl2_plat_arch_setup(void) { ls_setup_page_tables(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL_CODE_BASE, BL_CODE_END, BL_RO_DATA_BASE, BL_RO_DATA_END #if USE_COHERENT_MEM , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif ); #ifdef AARCH32 enable_mmu_svc_mon(0); #else enable_mmu_el1(0); #endif }
void bl32_plat_enable_mmu(uint32_t flags) { enable_mmu_el1(flags); }