void AllJoyn_Start() {
AJ_Status status = AJ_OK;
AJ_AlwaysPrintf(("AllJoyn Version %s\n", AJ_GetVersion()));
// status = AJ_WiFiScan(NULL, ScanResult, 32);
// if (status != AJ_OK) {
// AJ_AlwaysPrintf(("WiFi scan failed\n"));
// }
// status = ConfigureSoftAP();
esp_init(115200);
status = ConfigureWifi();
// esp_serial_proxy();
if (status == AJ_OK) {
// AJ_Initialize();
AJ_Main();
}
AJ_AlwaysPrintf(("Quitting\n"));
while (TRUE) {
}
}
extern void #MARK_init(void);
void init_extensions(void) {
ah_init();
addrtype_init();
comment_init();
2connmark_init();
conntrack_init();
2dscp_init();
2ecn_init();
esp_init();
hashlimit_init();
helper_init();
icmp_init();
iprange_init();
length_init();
limit_init();
mac_init();
multiport_init();
#2mark_init();
owner_init();
physdev_init();
pkttype_init();
policy_init();
realm_init();
sctp_init();
standard_init();
state_init();
tcp_init();
2tcpmss_init();
2tos_init();
2ttl_init();
udp_init();
unclean_init();
CLASSIFY_init();
CONNMARK_init();
DNAT_init();
LOG_init();
#DSCP_init();
ECN_init();
MASQUERADE_init();
MIRROR_init();
NETMAP_init();
NFQUEUE_init();
NOTRACK_init();
REDIRECT_init();
REJECT_init();
#MARK_init();
}
int main(int argc, char **argv)
{
esp_init("test1", false);
for (int i = 0; i < 1000; i++){
esp_zone("outer");
//SimpleFunction();
std::this_thread::sleep_for(std::chrono::milliseconds(1));
esp_end();
esp_frame_end();
}
esp_shutdown();
return 0;
}
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
MachineState *machine)
{
const char *cpu_model = machine->cpu_model;
unsigned int i;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
qemu_irq esp_reset, dma_enable;
qemu_irq fdc_tc;
qemu_irq *cpu_halt;
unsigned long kernel_size;
DriveInfo *fd[MAX_FD];
FWCfgState *fw_cfg;
unsigned int num_vsimms;
/* init CPUs */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
for(i = 0; i < smp_cpus; i++) {
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
}
for (i = smp_cpus; i < MAX_CPUS; i++)
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
/* set up devices */
ram_init(0, machine->ram_size, hwdef->max_mem);
/* models without ECC don't trap when missing ram is accessed */
if (!hwdef->ecc_base) {
empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
}
prom_init(hwdef->slavio_base, bios_name);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
cpu_irqs);
for (i = 0; i < 32; i++) {
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
}
for (i = 0; i < MAX_CPUS; i++) {
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
}
if (hwdef->idreg_base) {
idreg_init(hwdef->idreg_base);
}
if (hwdef->afx_base) {
afx_init(hwdef->afx_base);
}
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
slavio_irq[30]);
if (hwdef->iommu_pad_base) {
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software shouldn't use aliased addresses, neither should it crash
when does. Using empty_slot instead of aliasing can help with
debugging such accesses */
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
}
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
iommu, &espdma_irq, 0);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[16], iommu, &ledma_irq, 1);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
exit (1);
}
num_vsimms = 0;
if (num_vsimms == 0) {
if (vga_interface_type == VGA_CG3) {
if (graphic_depth != 8) {
error_report("Unsupported depth: %d", graphic_depth);
exit(1);
}
if (!(graphic_width == 1024 && graphic_height == 768) &&
!(graphic_width == 1152 && graphic_height == 900)) {
error_report("Unsupported resolution: %d x %d", graphic_width,
graphic_height);
exit(1);
}
/* sbus irq 5 */
cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
} else {
/* If no display specified, default to TCX */
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
exit(1);
}
if (!(graphic_width == 1024 && graphic_height == 768)) {
error_report("Unsupported resolution: %d x %d",
graphic_width, graphic_height);
exit(1);
}
tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
}
}
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
/* vsimm registers probed by OBP */
if (hwdef->vsimm[i].reg_base) {
empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
}
}
if (hwdef->sx_base) {
empty_slot_init(hwdef->sx_base, 0x2000);
}
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
if (hwdef->apc_base) {
apc_init(hwdef->apc_base, cpu_halt[0]);
}
if (hwdef->fd_base) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
&fdc_tc);
} else {
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
}
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
slavio_irq[30], fdc_tc);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, &esp_reset, &dma_enable);
qdev_connect_gpio_out(espdma, 0, esp_reset);
qdev_connect_gpio_out(espdma, 1, dma_enable);
if (hwdef->cs_base) {
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
slavio_irq[5]);
}
if (hwdef->dbri_base) {
/* ISDN chip with attached CS4215 audio codec */
/* prom space */
empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
/* reg space */
empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
}
if (hwdef->bpp_base) {
/* parallel port */
empty_slot_init(hwdef->bpp_base, 0x20);
}
kernel_size = sun4m_load_kernel(machine->kernel_filename,
machine->initrd_filename,
machine->ram_size);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
machine->boot_order, machine->ram_size, kernel_size,
graphic_width, graphic_height, graphic_depth,
hwdef->nvram_machine_id, "Sun4m");
if (hwdef->ecc_base)
ecc_init(hwdef->ecc_base, slavio_irq[28],
hwdef->ecc_version);
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
machine->kernel_cmdline);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
unsigned int i;
void *iommu, *espdma, *ledma, *main_esp, *nvram;
qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
unsigned long prom_offset, kernel_size;
int ret;
char buf[1024];
BlockDriverState *fd[MAX_FD];
int index;
/* init CPU */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);
}
cpu_sparc_set_id(env, 0);
qemu_register_reset(main_cpu_reset, env);
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
env->prom_addr = hwdef->slavio_base;
/* allocate RAM */
if ((uint64_t)RAM_size > hwdef->max_mem) {
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
(unsigned int)RAM_size / (1024 * 1024),
(unsigned int)hwdef->max_mem / (1024 * 1024));
exit(1);
}
cpu_register_physical_memory(0, RAM_size, 0);
/* load boot prom */
prom_offset = RAM_size + hwdef->vram_size;
cpu_register_physical_memory(hwdef->slavio_base,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
if (ret < 0 || ret > PROM_SIZE_MAX)
ret = load_image(buf, phys_ram_base + prom_offset);
if (ret < 0 || ret > PROM_SIZE_MAX) {
fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
exit(1);
}
prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
/* set up devices */
slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
&slavio_irq, cpu_irqs);
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
slavio_irq[hwdef->me_irq]);
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
iommu, &espdma_irq, &esp_reset);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
&le_reset);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].model == NULL
|| strcmp(nd_table[0].model, "lance") == 0) {
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
} else if (strcmp(nd_table[0].model, "?") == 0) {
fprintf(stderr, "qemu: Supported NICs: lance\n");
exit (1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 2);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
nographic);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
serial_hds[1], serial_hds[0]);
if (hwdef->fd_base != (target_phys_addr_t)-1) {
/* there is zero or one floppy drive */
fd[1] = fd[0] = NULL;
index = drive_get_index(IF_FLOPPY, 0, 0);
if (index != -1)
fd[0] = drives_table[index].bdrv;
sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
}
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
esp_reset);
for (i = 0; i < ESP_MAX_DEVS; i++) {
index = drive_get_index(IF_SCSI, 0, i);
if (index == -1)
continue;
esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
}
kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
initrd_filename);
nvram_init((m48t59_t *)nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
boot_device, RAM_size, kernel_size, graphic_width,
graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
}
static
void mips_jazz_init (ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
CPUState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
int s_rtc, s_dma_dummy;
NICInfo *nd;
PITState *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
cpu_model = "24Kf";
#endif
}
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
qemu_register_reset(main_cpu_reset, env);
/* allocate RAM */
ram_offset = qemu_ram_alloc(ram_size);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
cpu_register_physical_memory(0xfff00000LL,
MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
qemu_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
/* ISA devices */
i8259 = i8259_init(env->irq[4]);
isa_bus_new(NULL);
isa_bus_irqs(i8259);
DMA_init(0);
pit = pit_init(0x40, i8259[0]);
pcspk_init(pit);
/* ISA IO space at 0x90000000 */
isa_mmio_init(0x90000000, 0x01000000);
isa_mem_base = 0x11000000;
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0);
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = qemu_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, rc4030[4],
rc4030_opaque, rc4030_dma_memory_rw);
break;
} else if (strcmp(nd->model, "?") == 0) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
rc4030[5], &esp_reset);
/* Floppy */
if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
fprintf(stderr, "qemu: too many floppy drives\n");
exit(1);
}
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
/* Real time clock */
rtc_init(1980);
s_rtc = cpu_register_io_memory(rtc_read, rtc_write, NULL);
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
/* Serial ports */
if (serial_hds[0])
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
if (serial_hds[1])
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
/* Sound card */
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
#ifdef HAS_AUDIO
audio_init(i8259);
#endif
/* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
ds1225y_init(0x80009000, "nvram");
/* LED indicator */
jazz_led_init(0x8000f000);
}
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
IOMMUMemoryRegion *rc4030_dma_mr;
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Chipset returns 0 in invalid reads and do not raise data exceptions.
* However, we can't simply add a global memory region to catch
* everything, as memory core directly call unassigned_mem_read/write
* on some invalid accesses, which call do_unassigned_access on the
* CPU, which raise an exception.
* Handle that case by hijacking the do_unassigned_access method on
* the CPU, and do not raise exceptions for data access. */
cc = CPU_GET_CLASS(cpu);
real_do_unassigned_access = cc->do_unassigned_access;
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
machine->ram_size);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
sysbus_connect_irq(sysbus, 0, env->irq[6]);
sysbus_connect_irq(sysbus, 1, env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(address_space, 0x90000000, isa_io);
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
&error_fatal);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
/* Floppy */
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0,
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env, *envs[MAX_CPUS];
unsigned int i;
void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
*espdma_irq, *ledma_irq;
qemu_irq *esp_reset, *le_reset;
unsigned long prom_offset, kernel_size;
int ret;
char buf[1024];
int index;
/* init CPUs */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
for (i = 0; i < smp_cpus; i++) {
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
exit(1);
}
cpu_sparc_set_id(env, i);
envs[i] = env;
if (i == 0) {
qemu_register_reset(main_cpu_reset, env);
} else {
qemu_register_reset(secondary_cpu_reset, env);
env->halted = 1;
}
register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
env->prom_addr = hwdef->slavio_base;
}
for (i = smp_cpus; i < MAX_CPUS; i++)
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
/* allocate RAM */
if ((uint64_t)RAM_size > hwdef->max_mem) {
fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
(unsigned int)RAM_size / (1024 * 1024),
(unsigned int)(hwdef->max_mem / (1024 * 1024)));
exit(1);
}
cpu_register_physical_memory(0, RAM_size, 0);
/* load boot prom */
prom_offset = RAM_size + hwdef->vram_size;
cpu_register_physical_memory(hwdef->slavio_base,
(PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
TARGET_PAGE_MASK,
prom_offset | IO_MEM_ROM);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
if (ret < 0 || ret > PROM_SIZE_MAX)
ret = load_image(buf, phys_ram_base + prom_offset);
if (ret < 0 || ret > PROM_SIZE_MAX) {
fprintf(stderr, "qemu: could not load prom '%s'\n",
buf);
exit(1);
}
/* set up devices */
sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
for (i = 0; i < MAX_IOUNITS; i++)
if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
iounits[i] = iommu_init(hwdef->iounit_bases[i],
hwdef->iounit_version,
sbi_irq[hwdef->me_irq]);
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
iounits[0], &espdma_irq, &esp_reset);
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
iounits[0], &ledma_irq, &le_reset);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].model == NULL
|| strcmp(nd_table[0].model, "lance") == 0) {
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
} else if (strcmp(nd_table[0].model, "?") == 0) {
fprintf(stderr, "qemu: Supported NICs: lance\n");
exit (1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
exit (1);
}
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
hwdef->nvram_size, 8);
slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
sbi_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
nographic);
// Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
// Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
serial_hds[1], serial_hds[0]);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq,
esp_reset);
for (i = 0; i < ESP_MAX_DEVS; i++) {
index = drive_get_index(IF_SCSI, 0, i);
if (index == -1)
continue;
esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
}
kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
initrd_filename);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
boot_device, RAM_size, kernel_size, graphic_width,
graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
}
int main(int argc, char *argv[])
#endif
{
#if !defined(SINGLE_PHASE)
int ch;
static struct phase_parms_s *phase;
static struct phase_nv_parms_s const *phase_nv;
#endif
static int32_t x;
int i;
#if !defined(__MSP430__)
if (start_host_environment(argc, argv) < 0)
exit(2);
#endif
system_setup();
#if !defined(ESP_SUPPORT) && defined(PHASE_CORRECTION_SUPPORT) && !defined(DYNAMIC_PHASE_CORRECTION_SUPPORT)
#if !defined(SINGLE_PHASE)
for (ch = 0; ch < NUM_PHASES; ch++)
{
phase = &chan[ch];
phase_nv = &nv_parms.seg_a.s.chan[ch];
#endif
#if defined(__MSP430_HAS_ADC12__) || defined(__MSP430_HAS_ADC10__)
set_phase_correction(&phase->metrology.current.in_phase_correction[0], phase_nv->current.phase_correction[0]);
#if GAIN_STAGES > 1
set_phase_correction(&phase->metrology.current.in_phase_correction[1], phase_nv->current.phase_correction[1]);
#endif
#if defined(SINGLE_PHASE) && defined(NEUTRAL_MONITOR_SUPPORT)
set_phase_correction(&phase->neutral.in_phase_correction[0], nv_parms.seg_a.s.neutral.phase_correction[0]);
#if GAIN_STAGES > 1
set_phase_correction(&phase->neutral.in_phase_correction[1], nv_parms.seg_a.s.neutral.phase_correction[1]);
#endif
#endif
#else
#if defined(SINGLE_PHASE)
set_sd16_phase_correction(&phase->metrology.current.in_phase_correction[0], 0, phase_nv->current.phase_correction[0]);
#if defined(NEUTRAL_MONITOR_SUPPORT)
set_sd16_phase_correction(&phase->metrology.neutral.in_phase_correction[0], 1, nv_parms.seg_a.s.neutral.phase_correction[0]);
#endif
#else
set_sd16_phase_correction(&phase->metrology.current.in_phase_correction[0], ch, phase_nv->current.phase_correction[0]);
#endif
#endif
#if !defined(SINGLE_PHASE)
}
#endif
#endif
#if defined(ESP_SUPPORT)
esp_init();
esp_start_measurement();
#endif
#if defined(MULTI_RATE_SUPPORT)
tariff_initialise();
#endif
send_message(0, 1);
for (;;)
{
kick_watchdog();
#if !defined(__MSP430__)
/* In the host environment we need to simulate interrupts here */
adc_interrupt();
#endif
#if !defined(SINGLE_PHASE)
phase = chan;
phase_nv = nv_parms.seg_a.s.chan;
for (ch = 0; ch < NUM_PHASES; ch++)
{
#endif
/* Unless we are in normal operating mode, we should wait to be
woken by a significant event from the interrupt routines. */
////#if 1 //// 0 //defined(__MSP430__)
//// if (operating_mode != OPERATING_MODE_NORMAL)
#ifdef USE_LPM
_BIS_SR(LPM0_bits);
#endif
#if defined(POWER_DOWN_SUPPORT)
if (operating_mode == OPERATING_MODE_POWERFAIL)
switch_to_powerfail_mode();
#endif
#if defined(LIMP_MODE_SUPPORT) && defined(IEC1107_SUPPORT)
if (nv_parms.seg_a.s.meter_uncalibrated)
enable_ir_receiver();
#endif
if ((phase->status & NEW_LOG))
{
/* The background activity has informed us that it is time to
perform a block processing operation. */
phase->status &= ~NEW_LOG;
#if defined(MAGNETIC_INTERFERENCE_SUPPORT)
if ((meter_status & STATUS_HIGH_MAGNETIC_FIELD))
{
/* The meter is suffering magnetic tampering, so continuously
charge for a great deal of electricity. */
x = phase->readings.V_rms*MAGNETIC_INTERFERENCE_CURRENT/(10*100);
}
else
#endif
//MM Added for LCD Fix; Start
#if defined(IHD430_SUPPORT)
RF_Tx[12]=total_active_power_array.uint8[0];
RF_Tx[13]=total_active_power_array.uint8[1];
RF_Tx[14]=total_active_power_array.uint8[2];
RF_Tx[15]=total_active_power_array.uint8[3];
RF_Tx[16] =0x28 ^ RF_Tx[12] ^ RF_Tx[13] ^ RF_Tx[14] ^ RF_Tx[15];
for (i=0; i<17; i++)
{
UCA2TXBUF=RF_Tx[i];
while(!(UCA2IFG&UCTXIFG));
}
#endif
lcd_display_mode++;
switch( lcd_display_mode )
{
case DISPLAY_VOLTAGE:
change_display=1;
temp= phase->readings.V_rms;
if (temp <0) temp=0;
LCDM1=0xC;
LCDM2=0x29;
break;
case DISPLAY_CURRENT:
change_display=1;
temp= phase->readings.I_rms;
if (temp <0) temp=0;
LCDM1=0x9C;
LCDM2=0x1;
//MM Take care of different decimal.
break;
case DISPLAY_ACTIVE_POWER:
change_display=1;
temp= phase->readings.active_power;
if (temp <0) temp=0;
LCDM1=0xCF;
LCDM2=0x1;
break;
case DISPLAY_REACTIVE_POWER:
change_display=1;
temp= phase->readings.reactive_power;
if (temp <0) temp=0;
LCDM1=0xC7;
LCDM2=0x3;
break;
case DISPLAY_APPARENT_POWER:
change_display=1;
temp= phase->readings.apparent_power;
if (temp <0) temp=0;
LCDM1=0xB7;
LCDM2=0x1;
break;
case DISPLAY_FREQUENCY:
change_display=1;
temp= phase->readings.frequency;
if (temp <0) temp=0;
LCDM1=0x8F;
LCDM2=0x1;
break;
case DISPLAY_POWER_FACTOR:
change_display=1;
temp= phase->readings.power_factor/10;
LCDM1=0x8F;
LCDM2=0x50;
if (temp < 0)
{
temp*= -1;
LCDM3=0x1C;
}
else
{
LCDM3= 0x9C;
}
LCDM3constant=1;
//Take negative and positive case for inductive and capacitive
break;
case DISPLAY_ACCUMULATED_POWER_TOTAL:
change_display=1;
temp= phase->consumed_active_energy/10;
LCDM1=0x9F;
LCDM2=0x1;
break;
default:
change_display=0;
break;
}
//temp=12345;
//total_active_power=0x12345;
// MM Comment back in to display active power
// if (total_active_power <0)
// temp=-(total_active_power);
// else
// temp=total_active_power;
//MM Comment in two lines below for counter test //temp=12345;
// temp2++;
// temp=temp2;
if(change_display)
{
// LCDM1 = 0;
// LCDM2 = 0;
if(!LCDM3constant)
{
LCDM3 = 0;
}
else
{
LCDM3constant=0;
}
LCDM4 = 0;
LCDM5 = 0;
LCDM6 = 0;
LCDM7 = 0;
LCDM8 = 0;
LCDM9 = 0;
LCDM10 = 0;
LCDM11 = 0;
LCDM12 = 0;
LCDM13 = 0;
LCDM14 = 0;
LCDM15 = 0;
LCDM16 = 0;
LCDM17 = 0;
LCDM18 = 0;
LCDM19 = 0;
LCDM20 = 0;
thou_thou=0;
hun_thou=0;
ten_thou=0;
thou=0;
hun=0;
ten=0;
unit=0;
while (temp >=1000000)
{
thou_thou++;
temp-=1000000;
}
while (temp >=100000)
{
hun_thou++;
temp-=100000;
}
while (temp >=10000)
{
ten_thou++;
temp-=10000;
}
while (temp >=1000)
{
thou++;
temp-=1000;
}
while (temp >=100)
{
hun++;
temp-=100;
}
while (temp >=10)
{
ten++;
temp-=10;
}
while (temp >=1)
{
unit++;
temp--;
}
//MM: LCD fix to display higher active power readings
if(thou_thou)
{
LCDM11 = LCD_Char_Map[hun];
LCDM9 = LCD_Char_Map[thou];
//LCDM8 = 0x1;
LCDM7 = LCD_Char_Map[ten_thou];
LCDM5 = LCD_Char_Map[hun_thou];
LCDM3 = LCD_Char_Map[thou_thou];
}
else if(hun_thou)
{
LCDM11 = LCD_Char_Map[ten];
if (lcd_display_mode==DISPLAY_CURRENT) LCDM8 = 0x1;
else if(lcd_display_mode!=DISPLAY_ACCUMULATED_POWER_TOTAL) LCDM10 = 0x1; //MM do nothing
LCDM9 = LCD_Char_Map[hun];
LCDM7 = LCD_Char_Map[thou];
LCDM5 = LCD_Char_Map[ten_thou];
LCDM3 = LCD_Char_Map[hun_thou];
}
else
{
LCDM11 = LCD_Char_Map[unit];
LCDM9 = LCD_Char_Map[ten];
if (lcd_display_mode==DISPLAY_CURRENT || lcd_display_mode==DISPLAY_POWER_FACTOR)
{
LCDM6 = 0x1;
}
else if(lcd_display_mode==DISPLAY_ACCUMULATED_POWER_TOTAL)
{
LCDM10 = 0x1;
}
else
{
LCDM8 = 0x1;
}
if (lcd_display_mode!=DISPLAY_POWER_FACTOR)
{
LCDM3 = LCD_Char_Map[ten_thou];
}
LCDM7 = LCD_Char_Map[hun];
LCDM5 = LCD_Char_Map[thou];
}
if (lcd_display_mode==DISPLAY_ACCUMULATED_POWER_TOTAL)
{
lcd_display_mode=-2;
}
}
//MM end
if (operating_mode == OPERATING_MODE_NORMAL)
{
/* We can only do real power assessment in full operating mode */
#if !defined(SINGLE_PHASE)
x = active_power(phase, phase_nv);
#if defined(PRECALCULATED_PARAMETER_SUPPORT)
#if defined(IRMS_SUPPORT)
phase->readings.I_rms = current(phase, phase_nv, ch);
#endif
#if defined(VRMS_SUPPORT)
phase->readings.V_rms = voltage(phase, phase_nv);
#endif
#endif
#else
x = active_power();
#if defined(PRECALCULATED_PARAMETER_SUPPORT)
#if defined(IRMS_SUPPORT)
phase->readings.I_rms = current();
#endif
#if defined(VRMS_SUPPORT)
phase->readings.V_rms = voltage();
#endif
#endif
#endif
}
#if defined(LIMP_MODE_SUPPORT)
else if (operating_mode == OPERATING_MODE_LIMP)
{
/* In limp mode we must assess estimated power from only the measured current. */
/* We cannot properly determine current reversal in this mode. Also, current
imbalance is really just a measure of which lead is still connected.
Just treat both the imbalance and reversal conditions as OK */
#if !defined(SINGLE_PHASE)
x = current(phase, phase_nv, ch);
#if defined(PRECALCULATED_PARAMETER_SUPPORT) && defined(VRMS_SUPPORT)
phase->readings.V_rms = voltage(phase, phase_nv);
#endif
#else
x = current();
#if defined(PRECALCULATED_PARAMETER_SUPPORT) && defined(VRMS_SUPPORT)
phase->readings.V_rms = voltage();
#endif
#endif
#if defined(PRECALCULATED_PARAMETER_SUPPORT) && defined(IRMS_SUPPORT)
phase->readings.I_rms = x;
#endif
x = x*MAINS_NOMINAL_VOLTAGE/10;
}
#endif
if (labs(x) < RESIDUAL_POWER_CUTOFF || (phase->status & V_OVERRANGE))
{
x = 0;
#if defined(PRECALCULATED_PARAMETER_SUPPORT) && defined(IRMS_SUPPORT)
/* Avoid displaying a residual current, which is nothing more
than integrated noise. */
//phase->I_rms = 0;
#endif
/* Turn off the LEDs, regardless of the internal state of the
reverse and imbalance assessments. */
#if defined(PHASE_REVERSED_DETECTION_SUPPORT)
meter_status &= ~STATUS_REVERSED;
clr_reverse_current_indicator();
#endif
#if defined(POWER_BALANCE_DETECTION_SUPPORT)
meter_status &= ~STATUS_EARTHED;
clr_earthed_indicator();
#endif
}
else
{
if (operating_mode == OPERATING_MODE_NORMAL)
{
#if defined(PHASE_REVERSED_DETECTION_SUPPORT) && defined(PHASE_REVERSED_IS_TAMPERING)
if ((phase->status & PHASE_REVERSED))
{
meter_status |= STATUS_REVERSED;
set_reverse_current_indicator();
}
else
{
meter_status &= ~STATUS_REVERSED;
clr_reverse_current_indicator();
}
#endif
#if defined(POWER_BALANCE_DETECTION_SUPPORT)
if ((phase->status & PHASE_UNBALANCED))
{
meter_status |= STATUS_EARTHED;
set_earthed_indicator();
}
else
{
meter_status &= ~STATUS_EARTHED;
clr_earthed_indicator();
}
#endif
}
#if defined(LIMP_MODE_SUPPORT)
else
{
#if defined(PHASE_REVERSED_DETECTION_SUPPORT)
/* We cannot tell forward from reverse current in limp mode,
so just say it is not reversed. */
meter_status &= ~STATUS_REVERSED;
clr_reverse_current_indicator();
#endif
#if defined(POWER_BALANCE_DETECTION_SUPPORT)
/* We are definitely in the unbalanced state, but only set
the indicator if we have persistence checked, and the current
is sufficient to sustain operation. */
if ((phase->status & PHASE_UNBALANCED) && phase->readings.I_rms >= LIMP_MODE_MINIMUM_CURRENT)
{
meter_status |= STATUS_EARTHED;
set_earthed_indicator();
}
else
{
meter_status &= ~STATUS_EARTHED;
clr_earthed_indicator();
}
#endif
/* Only run the IR interface if we are sure there is enough power from the
supply to support the additional current drain. If we have not yet been
calibrated we had better keep the IR port running so we can complete the
calibration. */
#if defined(LIMP_MODE_SUPPORT) && defined(IEC1107_SUPPORT)
if (phase->I_rms >= LIMP_MODE_MINIMUM_CURRENT_FOR_IR
||
nv_parms.seg_a.s.meter_uncalibrated)
{
enable_ir_receiver();
}
else
{
disable_ir_receiver();
}
#endif
}
#endif
}
//x /= 10;
#if defined(SINGLE_PHASE) && defined(TOTAL_ACTIVE_ENERGY_SUPPORT)
total_active_power = x;
#else
total_active_power += (x - phase->readings.active_power);
#endif
#if defined(PHASE_REVERSED_DETECTION_SUPPORT) && defined(PHASE_REVERSED_IS_GENERATION)
#endif
#if defined(IHD430_SUPPORT)
total_active_power_array.uint32=total_active_power;
#endif
phase->readings.active_power = x;
#if defined(PRECALCULATED_PARAMETER_SUPPORT)
#if defined(REACTIVE_POWER_SUPPORT)
#if defined(SINGLE_PHASE)
x = reactive_power();
#else
x = reactive_power(phase, phase_nv);
#endif
#if defined(SINGLE_PHASE) && defined(TOTAL_REACTIVE_ENERGY_SUPPORT)
total_reactive_power = x;
#else
total_reactive_power += (x - phase->readings.reactive_power);
#endif
phase->readings.reactive_power = x;
#endif
#if defined(APPARENT_POWER_SUPPORT)
#if defined(SINGLE_PHASE)
phase->readings.apparent_power = apparent_power();
#else
phase->readings.apparent_power = apparent_power(phase, phase_nv);
#endif
#endif
#if defined(POWER_FACTOR_SUPPORT)
/* The power factor should be calculated last */
#if defined(SINGLE_PHASE)
phase->readings.power_factor = power_factor();
#else
phase->readings.power_factor = power_factor(phase, phase_nv);
#endif
#endif
#endif
#if defined(PER_PHASE_ACTIVE_ENERGY_SUPPORT)
// phase->active_energy_counter += x*phase->metrology.dot_prod_logged.sample_count;
// while (phase->active_energy_counter > ENERGY_WATT_HOUR_THRESHOLD)
// {
// phase->active_energy_counter -= ENERGY_WATT_HOUR_THRESHOLD;
// phase->consumed_active_energy++;
// }
#endif
#if defined(PRECALCULATED_PARAMETER_SUPPORT) && defined(MAINS_FREQUENCY_SUPPORT)
#if defined(SINGLE_PHASE)
phase->readings.frequency = frequency();
#else
phase->readings.frequency = frequency(phase, phase_nv);
#endif
#endif
#if defined(MAGNETIC_INTERFERENCE_SUPPORT)
#if !defined(SINGLE_PHASE)
if (ch == 0)
#endif
{
if ((meter_status & STATUS_HIGH_MAGNETIC_FIELD))
{
if (phase->sample_count_logged/magnetic_sensor_count_logged < MAGNETIC_INTERFERENCE_SAMPLE_RATIO)
{
if (--magnetic_interference_persistence <= -MAGNETIC_INTERFERENCE_PERSISTENCE_CHECK)
{
meter_status &= ~STATUS_HIGH_MAGNETIC_FIELD;
magnetic_interference_persistence = 0;
}
}
else
{
magnetic_interference_persistence = 0;
}
}
else
{
if (phase->sample_count_logged/magnetic_sensor_count_logged >= MAGNETIC_INTERFERENCE_SAMPLE_RATIO)
{
if (++magnetic_interference_persistence >= MAGNETIC_INTERFERENCE_PERSISTENCE_CHECK)
{
meter_status |= STATUS_HIGH_MAGNETIC_FIELD;
magnetic_interference_persistence = 0;
}
}
else
{
magnetic_interference_persistence = 0;
}
}
}
#endif
}
#if defined(LIMP_MODE_SUPPORT)
/* The voltage channel DC estimate will never move very much when the
meter is operating normally. If it does move, there must be some
tampering, such as a diode between the grid and the meter. */
if (operating_mode == OPERATING_MODE_NORMAL)
{
if (phase->readings.V_rms < LIMP_MODE_VOLTAGE_THRESHOLD*100
||
phase->metrology.V_dc_estimate[0] > UPPER_TAMPER_V_DC_ESTIMATE
||
phase->metrology.V_dc_estimate[0] < LOWER_TAMPER_V_DC_ESTIMATE)
{
switch_to_limp_mode();
}
}
else if (operating_mode == OPERATING_MODE_LIMP)
{
if (phase->readings.V_rms >= NORMAL_MODE_VOLTAGE_THRESHOLD*100
&&
phase->metrology.V_dc_estimate[1] <= UPPER_LIMP_TAMPER_V_DC_ESTIMATE
&&
phase->metrology.V_dc_estimate[1] >= LOWER_LIMP_TAMPER_V_DC_ESTIMATE)
{
/* The LCD might need to be revived */
#if defined(__MSP430__)
LCDawaken();
#else
/* Tell the world we are ready to start */
#endif
switch_to_normal_mode();
}
}
#endif
#if !defined(SINGLE_PHASE)
phase++;
phase_nv++;
}
#endif
#if !defined(SINGLE_PHASE) && defined(NEUTRAL_MONITOR_SUPPORT) && defined(IRMS_SUPPORT)
if ((neutral.status & NEW_LOG))
{
/* The background activity has informed us that it is time to
perform a block processing operation. */
neutral.status &= ~NEW_LOG;
neutral.readings.I_rms = neutral_current();
}
#endif
#if defined(MULTI_RATE_SUPPORT)
tariff_management();
#endif
/* Do display and other housekeeping here */
if ((meter_status & TICKER))
{
/* Two seconds have passed */
/* We have a 2 second tick */
meter_status &= ~TICKER;
#if defined(__MSP430__) && defined(BASIC_LCD_SUPPORT)
/* Update the display, cycling through the phases */
update_display();
#endif
custom_2second_handler();
#if (defined(RTC_SUPPORT) || defined(CUSTOM_RTC_SUPPORT)) && defined(CORRECTED_RTC_SUPPORT)
correct_rtc();
#endif
}
custom_keypad_handler();
custom_mainloop_handler();
#if defined(MESH_NET_SUPPORT)
if (rf_service)
{
rf_service = 0;
rf_tick_service();
}
#endif
}
#if !defined(__AQCOMPILER__) && !defined(__IAR_SYSTEMS_ICC__)
return 0;
#endif
}
int main(void)
{
//! [setup_init]
system_init();
//延时、串口初始化
delay_init();
configure_usart();
configure_usart1();
//配置输入输出变量
port_get_config_defaults(&pini);
port_get_config_defaults(&pinc);
pinc.direction = PORT_PIN_DIR_OUTPUT;
//延时20s，使MQ2、MQ7充分初始化
delay_s(20);
//MQ2、MQ7初始化输出模拟电压值
mq2_init_value = mq_run(MQ2);
mq7_init_value = mq_run(MQ7);
//对ESP8266进行WIFI配置初始化
esp_init();
//! [setup_init]
//port_group_set_output_level(LED_0_PIN, LED_0_ACTIVE);
//! [main]
//定义串口接收变量，用户端口号
uint16_t temp='H', user = '******';
//! [main_loop]
while (true) {
if(usart_read_wait(&usart_instance, &temp) == STATUS_OK)
{
delay_us(8);
if(temp == 'D')
{
while(usart_write_wait(&usart_inst1, 'T')!=STATUS_OK){}
if(usart_read_wait(&usart_instance, &temp) == STATUS_OK)
{
if(temp == ',')
{
while(usart_write_wait(&usart_inst1, 'E')!=STATUS_OK){}
if(usart_read_wait(&usart_instance, &temp) == STATUS_OK)
{
user = temp;
while(usart_write_wait(&usart_inst1, 'S')!=STATUS_OK){}
while(true)
{
if(usart_read_wait(&usart_instance, &temp) == STATUS_OK)
{
if(islower(temp))
{
while(usart_write_wait(&usart_inst1, 'T')!=STATUS_OK){}
Do(temp, user);
break;
}
}
}
}
}
}
}
}
}
//! [main]
}
static void mips_jazz_init(MemoryRegion *address_space,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUMIPSState *env;
qemu_irq *rc4030, *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
qemu_irq *cpu_exit_irq;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
cpu_model = "R4000";
#else
/* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
cpu_model = "24Kf";
#endif
}
cpu = cpu_mips_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* allocate RAM */
memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
vmstate_register_ram_global(ram);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
vmstate_register_ram_global(bios);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(env);
cpu_mips_clock_init(env);
/* Chipset */
rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
address_space);
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA devices */
isa_bus = isa_bus_new(NULL, address_space_io);
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* ISA IO space at 0x90000000 */
isa_mmio_init(0x90000000, 0x01000000);
isa_mem_base = 0x11000000;
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, rc4030[3]);
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
vmstate_register_ram_global(rom_mr);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
rc4030_opaque, rc4030_dma_memory_rw);
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
rc4030[5], &esp_reset, &dma_enable);
/* Floppy */
if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
fprintf(stderr, "qemu: too many floppy drives\n");
exit(1);
}
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
