C++ (Cpp) eth_set_pinmux Examples

Example #1

File: board-m3-reff16.c Project: Sophrinix/Meson-3-Kernel

//#define NET_EXT_CLK 1
static void __init eth_pinmux_init(void)
{
	
   CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,(3<<17));//reg6[17/18]=0
   #ifdef NET_EXT_CLK
       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_IN_GPIOY0_REG6_18, 0);
   #else
       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0);
   #endif
	
    //power hold
    //setbits_le32(P_PREG_AGPIO_O,(1<<8));
    //clrbits_le32(P_PREG_AGPIO_EN_N,(1<<8));
    //set_gpio_mode(GPIOA_bank_bit(4),GPIOA_bit_bit0_14(4),GPIO_OUTPUT_MODE);
    //set_gpio_val(GPIOA_bank_bit(4),GPIOA_bit_bit0_14(4),1);

    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);           // Disable the Ethernet clocks
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<3));     // desc endianess "same order" 
    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<2));     // ata endianess "little"
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));     // divide by 2 for 100M
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);            // enable Ethernet clocks
    udelay(100);

    // ethernet reset
    set_gpio_mode(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), GPIO_OUTPUT_MODE);
    set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 0);
    mdelay(100);
    set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 1);
}

Example #2

File: m3_mbox.c Project: RoelandK/Amlogic-reff16-uboot

int board_eth_init(bd_t *bis)
{
	unsigned v;
	
	CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,(3<<17));//reg6[17/18]=0
#ifdef CONFIG_NET_CLK_EXTERNAL
	//rmii 50 in
	//set clock
    eth_clk_set_invert(7,50*CLK_1M,50*CLK_1M);
  eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_IN_GPIOY0_REG6_18, 0);
#else
	/* Use Misc PLL for the source of ethernet */
	eth_clk_set(ETH_CLKSRC_MISC_CLK, get_misc_pll_clk(), (50 * CLK_1M));
	/* Use Internal clock output from GPIOY0*/
	eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0);
#endif //CONFIG_NET_CLK_EXTERNAL
	
	/*disalbe*/
	//reset:LCD_G5
	writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks     
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
	writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order"   
	writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little"    
	writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M     
	writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL);  // enable Ethernet clocks   
	udelay(100);

	/* reset phy with GPIOD_7*/
	set_gpio_mode(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), GPIO_OUTPUT_MODE);
	set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 0);
	udelay(2000);    
	set_gpio_val(GPIOD_bank_bit0_9(7), GPIOD_bit_bit0_9(7), 1);
	udelay(2000);	//waiting reset end;
	
	/* reset phy with GPIOAO_6*/
/*	v = ~((1<<6)|(1<22));
	writel(v,0xC81000024);
	udelay(2000);   
	v |= (1<22);
	writel(v,0xC81000024);
	udelay(2000);	//waiting reset end;
	*/
    aml_eth_init(bis);
    return 0;
}

Example #3

File: m3_mid_reff07.c Project: Doxlon/buildroot-uboot

int board_eth_init(bd_t *bis)
{
	/* Use Misc PLL for the source of ethernet */
	eth_clk_set(ETH_CLKSRC_MISC_CLK, get_misc_pll_clk(), (50 * CLK_1M));
	/* Use Internal clock output from GPIOY0*/
	eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0);
	
	/*disalbe*/
	//reset:LCD_G5
	writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks     
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
	writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order"   
	writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little"    
	writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M     
	writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL);  // enable Ethernet clocks   
	udelay(100);

	/* reset phy with GPIOA_23*/
	set_gpio_mode(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), GPIO_OUTPUT_MODE);
	set_gpio_val(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), 0);
	udelay(100);    //GPIOE_bank_bit16_21(16) reset end;
	set_gpio_val(GPIOA_bank_bit0_27(23), GPIOA_bit_bit0_27(23), 1);
	udelay(100);	//waiting reset end;
    aml_eth_init(bis);
    return 0;
}

Example #4

File: aml_tv_m2c_2pc_4l_refe07.c Project: bogdanov-d-a/Amlogic-reff16-uboot

int board_eth_init(bd_t *bis)
{
    /*
    @todo implement this function
    */

    //eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);
    eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);
    // GPIOX59-X67 for M2_socket
    // GPIOE_57/NA nRst;
    eth_set_pinmux(ETH_BANK1_GPIOX59_X67,ETH_CLK_OUT_GPIOX68_REG3_14,0);

    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
    udelay(100);

    /*reset*/
    set_gpio_val(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), 0);
    set_gpio_mode(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), GPIO_OUTPUT_MODE);
    udelay(100);
    set_gpio_val(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), 1);
    set_gpio_mode(GPIOX_bank_bit32_63(57), GPIOX_bit_bit32_63(57), GPIO_OUTPUT_MODE);
    udelay(10);    //waiting reset end;
    aml_eth_init(bis);
    return 0;
}

Example #5

File: 8726m_mbx_refc07.c Project: Doxlon/buildroot-uboot

int board_eth_init(bd_t *bis)
{
    /*
    @todo implement this function
    */
          
  //  	eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);
	//eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);
	eth_clk_set(ETH_CLKSRC_APLL_CLK,400*CLK_1M,50*CLK_1M);
	///GPIOD15-24 for 8626M;
	///GPIOD12	nRst;
	///GPIOD13    n_int;
	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD24_REG5_1,0);
	/*disalbe*/
	//reset:LCD_G5
	writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks     
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
	writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order"   
	writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little"    
	writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M     
	writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL);  // enable Ethernet clocks   
	udelay(100);
	/*reset*/
	CLEAR_CBUS_REG_MASK(PREG_GGPIO_EN_N,1<<12);
	CLEAR_CBUS_REG_MASK(PREG_GGPIO_O,1<<12);
	udelay(100);
	SET_CBUS_REG_MASK(PREG_GGPIO_O,1<<12);
	udelay(10);	//waiting reset end;
	aml_eth_init(bis);
	return 0;
}

Example #6

File: 8726m_mid_refb09new.c Project: Doxlon/buildroot-uboot

static void gt2005_init(void)
{
	udelay(1000);
    SET_CBUS_REG_MASK(HHI_ETH_CLK_CNTL,0x30f);// 24M XTAL
    SET_CBUS_REG_MASK(HHI_DEMOD_PLL_CNTL,0x232);// 24M XTAL
    udelay(1000);

    eth_set_pinmux(ETH_BANK0_GPIOC3_C12,ETH_CLK_OUT_GPIOC12_REG3_1, 1);

	#ifdef CONFIG_EXIO_SN7325
	printk( "amlogic camera driver: init CONFIG_SN7325. \n");
	//PP1: 0 
    sn7325_set_io_dir(sn7325_get_io_dir() & ~PP1);
    sn7325_set_output_level(sn7325_get_output_level() & ~PP1);

	//PP2: 0 
    //sn7325_set_io_dir(sn7325_get_io_dir() & ~PP2);
    //sn7325_set_output_level(sn7325_get_output_level() & ~PP2);

	//PP0: 1 
    //sn7325_set_io_dir(sn7325_get_io_dir() & ~PP0);
    //sn7325_set_output_level(sn7325_get_output_level() | PP0);
	
	//PP6: 0 
    sn7325_set_io_dir(sn7325_get_io_dir() & ~PP6);
    sn7325_set_output_level(sn7325_get_output_level() & ~PP6);

    //OD3: 0  
    //sn7325_set_io_dir(sn7325_get_io_dir() & ~OD3);
    //sn7325_set_output_level(sn7325_get_output_level() & ~OD3);

    //OD2: 0  
    sn7325_set_io_dir(sn7325_get_io_dir() & ~OD2);
    sn7325_set_output_level(sn7325_get_output_level() & ~OD2);
	msleep(10);
	
    //PP1: 1
    sn7325_set_io_dir(sn7325_get_io_dir() & ~PP1);
    sn7325_set_output_level(sn7325_get_output_level() | PP1);
	msleep(10);

    //OD2: 1
    sn7325_set_io_dir(sn7325_get_io_dir() & ~OD2);
    sn7325_set_output_level(sn7325_get_output_level() | OD2);
	msleep(10);

    //PP6: 1
    sn7325_set_io_dir(sn7325_get_io_dir() & ~PP6);
    sn7325_set_output_level(sn7325_get_output_level() | PP6);
	msleep(20);
    #endif
}

Example #7

File: m1_8726m_ref.c Project: Doxlon/buildroot-uboot

int board_eth_init(bd_t *bis)
{
     int out;
    /*
    @todo implement this function
    */
	///GPIOD15-24 for 8626M;
	///GPIOD12	nRst;
	///GPIOD13    n_int;
	printf("Set 8626m\n");
	//eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);
	//eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);	
	eth_clk_set(ETH_CLKSRC_APLL_CLK,400*CLK_1M,50*CLK_1M);
	///GPIOD15-24 for 8626M;
	///GPIOD12	nRst;
	///GPIOD13    n_int;
	//eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD7_REG4_20,0);
	
	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD24_REG5_1,0);
	/*disalbe*/
	//reset:LCD_G5
	writel(readl(ETH_PLL_CNTL) & ~(1 << 0), ETH_PLL_CNTL); // Disable the Ethernet clocks     
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
	writel(readl(ETH_PLL_CNTL) | (0 << 3), ETH_PLL_CNTL); // desc endianess "same order"   
	writel(readl(ETH_PLL_CNTL) | (0 << 2), ETH_PLL_CNTL); // data endianess "little"    
	writel(readl(ETH_PLL_CNTL) | (1 << 1), ETH_PLL_CNTL); // divide by 2 for 100M     
	writel(readl(ETH_PLL_CNTL) | (1 << 0), ETH_PLL_CNTL);  // enable Ethernet clocks   
	udelay(100);
	/*reset*/
	//EIO P13 SET LOW
        out = hard_i2c_read8(EIO_ID, 0x01);
//        printf("out = %x\n", out);
        udelay(100);
	hard_i2c_write8(EIO_ID, 0x05, out&(~(0x8)));
	udelay(100);
        out = hard_i2c_read8(EIO_ID, 0x01);
//        printf("out2 = %x\n", out);
	//EIO P13 SET HIGH
	hard_i2c_write8(EIO_ID, 0x05, out|0x8);
	udelay(100);
//        out = hard_i2c_read8(EIO_ID, 0x01);
//        printf("out3 = %x\n", out);
	//power hold
//	setbits_le32(P_PREG_AGPIO_O,(1<<8));
//	clrbits_le32(P_PREG_AGPIO_EN_N,(1<<8));
	udelay(10);	//waiting reset end;
        aml_eth_init(bis);
        return 0;
}

Example #8

File: board-m3-reff16.c Project: J1nx-Hackable-Gadgets/buildroot-linux-kernel-m3

static void __init eth_pinmux_init(void)
{
	
   CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_6,(3<<17));//reg6[17/18]=0
   #ifdef NET_EXT_CLK
       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_IN_GPIOY0_REG6_18, 0);
   #else
       eth_set_pinmux(ETH_BANK0_GPIOY1_Y9, ETH_CLK_OUT_GPIOY0_REG6_17, 0);
   #endif
	
   CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);           // Disable the Ethernet clocks
	// ---------------------------------------------
	// Test 50Mhz Input Divide by 2
	// ---------------------------------------------
	// Select divide by 2
    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<3));     // desc endianess "same order" 
    CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1<<2));     // ata endianess "little"
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));     // divide by 2 for 100M
    SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);            // enable Ethernet clocks
    udelay(100);

    // ethernet reset
    meson_eth_reset();
}

Example #9

File: board-8626m-refc02.c Project: array92/zt280-kernel

static void __init eth_pinmux_init(void)
{

	/*for dpf_sz with ethernet*/	
		///GPIOD15-24 for 8626M;
	///GPIOE_16/NA	nRst;
	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD24_REG5_1,0);
	CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	udelay(100);
	/*reset*/
	set_gpio_mode(PREG_HGPIO,16,GPIO_OUTPUT_MODE);
	set_gpio_val(PREG_HGPIO,16,0);
	udelay(100);	//waiting reset end;
	set_gpio_val(PREG_HGPIO,16,1);
	udelay(10);	//waiting reset end;
}

Example #10

File: board-8726m-refc05.c Project: CoreTech-Development/buildroot-linux-kernel-m3

static void __init eth_pinmux_init(void)
{

	/*for dpf_sz with ethernet*/	
		///GPIOC17 -int
	///GPIOC19/NA	nRst;
	printk("eth pinmux init\n");
	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD24_REG5_1,0);
	CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	udelay(100);
	/*reset*/
	///GPIOC19/NA	nRst;
	set_gpio_mode(PREG_GGPIO,12,GPIO_OUTPUT_MODE);
	set_gpio_val(PREG_GGPIO,12,0);
	udelay(100);	//waiting reset end;
	set_gpio_val(PREG_GGPIO,12,1);
	udelay(10);	//waiting reset end;
}

Example #11

File: BGA372-M_SKT_V1.c Project: Doxlon/buildroot-uboot

int board_eth_init(bd_t *bis)
{
    /*
    @todo implement this function
    */
    //eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);
 	//eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);
	eth_clk_set(ETH_CLKSRC_APLL_CLK,400*CLK_1M,50*CLK_1M);
	/*for dpf_sz with ethernet*/	
    	eth_set_pinmux(ETH_BANK0_GPIOC3_C12,ETH_CLK_OUT_GPIOC12_REG3_1,0);
	CLEAR_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, (1 << 1));
	SET_CBUS_REG_MASK(PREG_ETHERNET_ADDR0, 1);
	udelay(100);
	/*reset*/
	CLEAR_CBUS_REG_MASK(PREG_FGPIO_EN_N,1<<0);
	CLEAR_CBUS_REG_MASK(PREG_FGPIO_O,1<<0);
	udelay(100);
	SET_CBUS_REG_MASK(PREG_FGPIO_O,1<<0);
	aml_eth_init(bis);
	return 0;
}

Example #12

File: 8726m_mid_refb09new.c Project: Doxlon/buildroot-uboot

int board_eth_init(bd_t *bis)
{
    /*
    @todo implement this function
    */
	///GPIOD15-24 for 8626M;
	///GPIOD12	nRst;
	///GPIOD13    n_int;
	printf("Set 8626m \n");
	//eth_clk_set(ETH_CLKSRC_SYS_D3,900*CLK_1M/3,50*CLK_1M);
	//eth_clk_set(ETH_CLKSRC_SYS_D3,get_cpu_clk()*2/3,50*CLK_1M);	
	eth_clk_set(ETH_CLKSRC_APLL_CLK,400*CLK_1M,50*CLK_1M);
	///GPIOD15-24 for 8626M;
	///GPIOD12	nRst;
	///GPIOD13    n_int;
	eth_set_pinmux(ETH_BANK2_GPIOD15_D23,ETH_CLK_OUT_GPIOD7_REG4_20,0);
	
	//power hold
	setbits_le32(P_PREG_AGPIO_O,(1<<8));
	clrbits_le32(P_PREG_AGPIO_EN_N,(1<<8));
	udelay(10);	//waiting reset end;
        aml_eth_init(bis);
        return 0;
}