/**
* sleep - most versatile sleep mode. SnoozeBlock configuration or any interrupt can wake the processor.
*
* @param configuration SnoozeBlock class config.
*
* @return wakeup source
*/
int SnoozeClass::sleep( SnoozeBlock &configuration ) {
SnoozeBlock *p = &configuration;
enable_periph_irq = true;
#ifdef KINETISL
tsi_set( &p->tsi_mask );
#endif
cmp_set( &p->cmp_mask );
lptmr_set( &p->lptmr_mask );
#ifdef KINETISK
rtc_alarm_set( &p->rtc_mask );
#endif
digital_set( &p->digital_mask );
#ifdef KINETISL
pinMode( 17, OUTPUT );
digitalWriteFast( 17, LOW );
#endif
if ( mcg_mode( ) == BLPI ) {
peripheral_disable( &p->setPeripheral.periph_off_mask );
enter_wait( );
peripheral_set( &p->setPeripheral.periph_off_mask );
}
else if ( mcg_mode( ) == BLPE ) {
peripheral_set( &p->setPeripheral.periph_off_mask );
blpe_blpi ( );
enter_vlpr( 0 );// now safe to enter vlpr
enter_wait( );
exit_vlpr ( );
blpi_blpe ( );
peripheral_set( &p->setPeripheral.periph_off_mask );
}
else {
peripheral_set( &p->setPeripheral.periph_off_mask );
usbDisable( );
pee_blpi ( );
enter_vlpr( 0 );// now safe to enter vlpr
enter_wait( );
exit_vlpr ( );
blpi_pee ( );
usbEnable ( );
peripheral_set( &p->setPeripheral.periph_off_mask );
}
digital_disable( &p->digital_mask );
#ifdef KINETISK
rtc_disable( &p->rtc_mask );
#endif
lptmr_disable( &p->lptmr_mask );
cmp_disable( &p->cmp_mask );
#ifdef KINETISL
tsi_disable( &p->tsi_mask );
#endif
return wakeupSource;
}
void init_hardware(void)
{
exit_vlpr();
// Enable all the ports
SIM->SCGC5 |= ( SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
}
void init_hardware(void)
{
exit_vlpr();
// Enable all the ports
SIM->SCGC5 |= ( SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; // Select IRC48M as various peripheral clock source
}
void init_hardware(void)
{
exit_vlpr();
// Enable all the ports
SIM->SCGC5 |= ( SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; // set PLLFLLSEL to select the IRC48M for this clock source
}
