static void __init exynos3250_cmu_init(struct device_node *np) { struct samsung_clk_provider *ctx; reg_base = of_iomap(np, 0); if (!reg_base) panic("%s: failed to map registers\n", __func__); ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); if (!ctx) panic("%s: unable to allocate context.\n", __func__); samsung_clk_register_fixed_factor(ctx, fixed_factor_clks, ARRAY_SIZE(fixed_factor_clks)); exynos3250_plls[apll].rate_table = exynos3250_pll_rates; exynos3250_plls[mpll].rate_table = exynos3250_pll_rates; exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates; exynos3250_plls[upll].rate_table = exynos3250_pll_rates; samsung_clk_register_pll(ctx, exynos3250_plls, ARRAY_SIZE(exynos3250_plls), reg_base); samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); exynos3_core_down_clock(); exynos3250_clk_sleep_init(); samsung_clk_of_add_provider(np, ctx); }
static void __init exynos3250_cmu_init(struct device_node *np) { struct samsung_clk_provider *ctx; ctx = samsung_cmu_register_one(np, &cmu_info); if (!ctx) return; exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", mout_core_p[0], mout_core_p[1], 0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), CLK_CPU_HAS_DIV1); exynos3_core_down_clock(ctx->reg_base); }