void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x42); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif /* Initialize i8259 pic */ post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x44); setup_i8254 (); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 reg8; // all cores: allow caching of flash chip code and data // (there are no cache-as-ram reliability concerns with family 14h) __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); if (boot_cpu()) { u8 reg8; // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register outb(0x24, 0xCD6); reg8 = inb(0xCD7); reg8 |= 1; reg8 &= ~(1 << 1); outb(reg8, 0xCD7); // program SB800 MiscCntrl *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ } // early enable of PrefetchEnSPIFromHost if (boot_cpu()) { __outdword (0xcf8, 0x8000a3b8); __outdword (0xcfc, __indword (0xcfc) | 1 << 24); } // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { volatile u32 *spiBase = (void *) 0xa0000000; u32 save; __outdword (0xcf8, 0x8000a3a0); save = __indword (0xcfc); __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14); spiBase [0] |= 1 << 18; // fast read enable __outdword (0xcfc, save); // clear temp base } if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); val = agesawrapper_amdinitmmio(); post_code(0x37); val = agesawrapper_amdinitreset(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } post_code(0x38); printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); post_code(0x39); val = agesawrapper_amdinitearly (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); post_code(0x40); val = agesawrapper_amdinitpost (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); post_code(0x41); val = agesawrapper_amdinitenv (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); /* Initialize i8259 pic */ post_code(0x41); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x42); setup_i8254 (); post_code(0x50); copy_and_run(0); post_code(0x54); // Should never see this post code. }