/* set frequency of PWM signal to freq */
int pwm_freq_set(int channel, u_int32_t freq)
{
/* in order to get maximum resolution, the pre-scaler must be set to
* something like freq << 16. However, the mimimum pre-scaled frequency
* we can get is MCLK (48MHz), the minimum is MCLK/(1024*255) =
* 48MHz/261120 = 183Hz */
u_int32_t overall_div;
u_int32_t presc_total;
u_int8_t cpre = 0;
u_int16_t cprd;
if (freq > MCLK)
return -ERANGE;
overall_div = MCLK / freq;
DEBUGPCRF("mclk=%u, freq=%u, overall_div=%u", MCLK, freq, overall_div);
if (overall_div > 0x7fff) {
/* divisor is larger than half the maximum CPRD register, we
* have to configure prescalers */
presc_total = overall_div >> 15;
/* find highest 2^n fitting in prescaler (highest bit set) */
cpre = fhs(presc_total);
if (cpre > 0) {
/* subtract one, because of fhs semantics */
cpre--;
}
cprd = overall_div / (1 << cpre);
} else
/* set frequency of PWM signal to freq */
int pwmFreqSet(int channel, uint32_t freq)
{
/* in order to get maximum resolution, the pre-scaler must be set to
* something like freq << 16. However, the mimimum pre-scaled frequency
* we can get is MCLK (48MHz), the minimum is MCLK/(1024*255) =
* 48MHz/261120 = 183Hz */
uint32_t overall_div;
uint32_t presc_total;
uint8_t cpre = 0;
uint16_t cprd;
if (freq > MCK)
return -1;
overall_div = MCK / freq;
if (overall_div > 0x7fff)
{
// divisor is larger than half the maximum CPRD register, we
// have to configure prescalers
presc_total = overall_div >> 15;
// find highest 2^n fitting in prescaler (highest bit set)
cpre = fhs(presc_total);
if (cpre > 0)
{
// subtract one, because of fhs semantics //
cpre--;
}
cprd = overall_div / (1 << cpre);
}