// Main interrupt handler, queries the interrupt controller to see what peripheral
// fired the interrupt and then dispatches the corresponding interrupt handler.
// This routine acks the interrupt at the controller level but the peripheral
// interrupt must be ack'd by the dispatched interrupt handler.
void interrupt_handler_dispatcher(void* ptr) {
int intc_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
// Check the FIT interrupt first.
if (intc_status & XPAR_FIT_TIMER_0_INTERRUPT_MASK){
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_FIT_TIMER_0_INTERRUPT_MASK);
timer_interrupt_handler();
}
// Check the push buttons.
if (intc_status & XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK){
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK);
pb_interrupt_handler();
}
// Check the FIFO-IN in the XAC97
if (intc_status & XPAR_AXI_AC97_0_INTERRUPT_MASK){
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_AXI_AC97_0_INTERRUPT_MASK);
fifo_interrupt_handler();
}
}
void interrupt_handler_dispatcher(void* ptr) {
// Ask the Interrupt Controller for a status of its interrupts
uint32_t status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
// Check what triggered the interrupt
if (status & XPAR_FIT_TIMER_0_INTERRUPT_MASK) {
// Let the timer know it got an interrupt!
// if (interrupts_timer_handler) interrupts_timer_handler();
// Then acknowledge it so it can interrupt again
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_FIT_TIMER_0_INTERRUPT_MASK);
} else if (status & XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK) {
// ----------
// Turn off all PB interrupts for now.
XGpio_InterruptGlobalDisable(&gpPB);
u32 currentButtonState = XGpio_DiscreteRead(&gpPB, 1);
pb_interrupt_handler(currentButtonState);
// XAC97_PlayAudio(XPAR_AXI_AC97_0_BASEADDR, sound_alienMove2.data, &sound_alienMove2.data[sound_alienMove2.numSamples]);
// Ack the PB interrupt.
XGpio_InterruptClear(&gpPB, 0xFFFFFFFF);
// Re-enable PB interrupts.
XGpio_InterruptGlobalEnable(&gpPB);
// ------
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK);
} else if (status & XPAR_AXI_AC97_0_INTERRUPT_MASK) {
fifo_interrupt_handler();
XIntc_AckIntr(XPAR_INTC_0_BASEADDR, XPAR_AXI_AC97_0_INTERRUPT_MASK);
}
}
