asmlinkage void *car_stage_c_entry(void) { post_code(0x20); if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { FSP_INFO_HEADER *fih; struct cache_as_ram_params car_params = {0}; void *top_of_stack; /* Copy the FSP binary into ESRAM */ memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, 0x00040000); /* Locate the FSP header in ESRAM */ fih = find_fsp(CONFIG_FSP_ESRAM_LOC); /* Start the early verstage/romstage code */ post_code(0x2A); car_params.fih = fih; top_of_stack = cache_as_ram_main(&car_params); /* Initialize MTRRs and switch stacks after RAM initialized */ return top_of_stack; } return NULL; }
void FspNotify (u32 Phase) { FSP_NOTFY_PHASE NotifyPhaseProc; NOTIFY_PHASE_PARAMS NotifyPhaseParams; EFI_STATUS Status; if (fsp_header_ptr == NULL) { fsp_header_ptr = (void *)find_fsp(); if ((u32)fsp_header_ptr < 0xff) { post_code(0x4F); /* output something in case there is no serial */ die("Can't find the FSP!\n"); } } /* call FSP PEI to Notify PostPciEnumeration */ NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase + fsp_header_ptr->NotifyPhaseEntry); NotifyPhaseParams.Phase = Phase; timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); Status = NotifyPhaseProc (&NotifyPhaseParams); timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); }
void fsp_notify(u32 phase) { FSP_NOTIFY_PHASE notify_phase_proc; NOTIFY_PHASE_PARAMS notify_phase_params; EFI_STATUS status; FSP_INFO_HEADER *fsp_header_ptr; fsp_header_ptr = fsp_get_fih(); if (fsp_header_ptr == NULL) { fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC); if ((u32)fsp_header_ptr < 0xff) { /* output something in case there is no serial */ post_code(0x4F); die("Can't find the FSP!\n"); } } /* call FSP PEI to Notify PostPciEnumeration */ notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase + fsp_header_ptr->NotifyPhaseEntryOffset); notify_phase_params.Phase = phase; timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); status = notify_phase_proc(¬ify_phase_params); timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); if (status != 0) printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", phase, status); }
void fsp_silicon_init(bool s3wake) { if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) intel_silicon_init(); else fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake); }
void print_fsp_info(void) { if (fsp_header_ptr == NULL) fsp_header_ptr = (void *)find_fsp(); if ((u32)fsp_header_ptr < 0xff) { post_code(0x4F); /* output something in case there is no serial */ die("Can't find the FSP!\n"); } if (FspHobListPtr == NULL) { FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); } printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr); printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision); printk(BIOS_INFO,"FSP Revision: %d.%d\n", (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff), (u8)(fsp_header_ptr->ImageRevision & 0xff)); }
/* Entry point taken when romstage is called after a separate verstage. */ asmlinkage void *romstage_after_verstage(void) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); console_init(); if (prog_locate(&fsp)) { fih = NULL; printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); } else /* This leaks a mapping which this code assumes is benign as * the flash is memory mapped CPU's address space. */ fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); set_fih_car(fih); /* Return new stack value in ram back to assembly stub. */ return cache_as_ram_stage_main(fih); }