static int fm3_erase(struct flash_bank *bank, int first, int last) { struct fm3_flash_bank *fm3_info = bank->driver_priv; struct target *target = bank->target; int retval = ERROR_OK; uint32_t u32DummyRead; int sector, odd; uint32_t u32FlashType; uint32_t u32FlashSeqAddress1; uint32_t u32FlashSeqAddress2; u32FlashType = (uint32_t) fm3_info->flashtype; if (u32FlashType == fm3_flash_type1) { u32FlashSeqAddress1 = 0x00001550; u32FlashSeqAddress2 = 0x00000AA8; } else if (u32FlashType == fm3_flash_type2) { u32FlashSeqAddress1 = 0x00000AA8; u32FlashSeqAddress2 = 0x00000554; } else { LOG_ERROR("Flash/Device type unknown!"); return ERROR_FLASH_OPERATION_FAILED; } if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } LOG_INFO("Fujitsu MB9Bxxx: Sector Erase ... (%d to %d)", first, last); /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */ retval = target_write_u32(target, 0x40000000, 0x0001); if (retval != ERROR_OK) return retval; /* dummy read of FASZR */ retval = target_read_u32(target, 0x40000000, &u32DummyRead); if (retval != ERROR_OK) return retval; for (sector = first ; sector <= last ; sector++) { uint32_t offset = bank->sectors[sector].offset; for (odd = 0; odd < 2 ; odd++) { if (odd) offset += 4; /* Flash unlock sequence */ retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress1, 0x0080); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055); if (retval != ERROR_OK) return retval; /* Sector erase command (0x0030) */ retval = target_write_u16(target, offset, 0x0030); if (retval != ERROR_OK) return retval; retval = fm3_busy_wait(target, offset, 500); if (retval != ERROR_OK) return retval; } bank->sectors[sector].is_erased = 1; } /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */ retval = target_write_u32(target, 0x40000000, 0x0002); if (retval != ERROR_OK) return retval; /* dummy read of FASZR */ retval = target_read_u32(target, 0x40000000, &u32DummyRead); return retval; }
/* Chip erase */ static int fm3_chip_erase(struct flash_bank *bank) { struct target *target = bank->target; struct fm3_flash_bank *fm3_info2 = bank->driver_priv; int retval = ERROR_OK; uint32_t u32DummyRead; uint32_t u32FlashType; uint32_t u32FlashSeqAddress1; uint32_t u32FlashSeqAddress2; u32FlashType = (uint32_t) fm3_info2->flashtype; if (u32FlashType == fm3_flash_type1) { LOG_INFO("*** Erasing mb9bfxxx type"); u32FlashSeqAddress1 = 0x00001550; u32FlashSeqAddress2 = 0x00000AA8; } else if (u32FlashType == fm3_flash_type2) { LOG_INFO("*** Erasing mb9afxxx type"); u32FlashSeqAddress1 = 0x00000AA8; u32FlashSeqAddress2 = 0x00000554; } else { LOG_ERROR("Flash/Device type unknown!"); return ERROR_FLASH_OPERATION_FAILED; } if (target->state != TARGET_HALTED) { LOG_ERROR("Target not halted"); return ERROR_TARGET_NOT_HALTED; } LOG_INFO("Fujitsu MB9[AB]xxx: Chip Erase ... (may take several seconds)"); /* Implement Flash chip erase (mass erase) completely on host */ /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */ retval = target_write_u32(target, 0x40000000, 0x0001); if (retval != ERROR_OK) return retval; /* dummy read of FASZR */ retval = target_read_u32(target, 0x40000000, &u32DummyRead); if (retval != ERROR_OK) return retval; /* Flash unlock sequence */ retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress1, 0x0080); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress1, 0x00AA); if (retval != ERROR_OK) return retval; retval = target_write_u16(target, u32FlashSeqAddress2, 0x0055); if (retval != ERROR_OK) return retval; /* Chip Erase command (0x0010) */ retval = target_write_u16(target, u32FlashSeqAddress1, 0x0010); if (retval != ERROR_OK) return retval; retval = fm3_busy_wait(target, u32FlashSeqAddress2, 20000); /* 20s timeout */ if (retval != ERROR_OK) return retval; /* FASZR = 0x02, Re-enables CPU Run Mode (32-bit Flash access) */ retval = target_write_u32(target, 0x40000000, 0x0002); if (retval != ERROR_OK) return retval; retval = target_read_u32(target, 0x40000000, &u32DummyRead); /* dummy read of FASZR */ return retval; }