/**
* Main entry point.
*/
int main(int argc, char* argv[])
{
fpga_dev * fpgaDev;
int rtn, channel, timeout;
unsigned int arg0, arg1;
struct timeval tv;
double tempTime;
timeout = 10*1000; // 10 secs.
channel = 1;
arg0 = (unsigned int)rand();
arg1 = (unsigned int)rand();
if ((rtn = fpga_init(&fpgaDev)) < 0) {
printf("error opening fpga: %d\n", rtn);
return rtn;
}
if ((rtn = fpga_channel_open(fpgaDev, channel, timeout)) < 0) {
printf("error opening fpga channel: %d\n", rtn);
return rtn;
}
printf("Opened.\n");
while (1) {
if ((rtn = fpga_send_args(fpgaDev, channel, arg0, arg1, 2, 1)) < 0) {
printf("error sending args to fpga: %d\n", rtn);
break;
}
printf("Called with args: 0x%x, 0x%x.\n", arg0, arg1);
gettimeofday(&tv, NULL);
tempTime = tv.tv_sec + tv.tv_usec / 1000000.0;
if ((rtn = fpga_recv_data(fpgaDev, channel, (unsigned char *)gData, DATA_SIZE)) < 0) {
printf("error receiving data from fpga: %d\n", rtn);
break;
}
gettimeofday(&tv, NULL);
tempTime = (tv.tv_sec + tv.tv_usec / 1000000.0) - tempTime;
printf("Duration: %f MBs: %f\n", tempTime, (rtn/tempTime)/(1024*1024));
printf("Received data response, length: %d (0x%x)\n", rtn, rtn);
printf("Values 1 & 2: 0x%x, 0x%x (from first half DMA transfer) should equal 0x%x, 0x%x\n",
gData[1], gData[2], arg0, arg1);
printf("Values 64KB + 1 & 64KB + 2: 0x%x, 0x%x (from second half DMA transfer) should equal 0x%x, 0x%x\n",
gData[(64*1024/4) + 1], gData[(64*1024/4) + 2], arg0, arg1);
break;
}
printf("Done.\n");
fpga_channel_close(fpgaDev, 0);
fpga_free(fpgaDev);
printf("Exiting.\n");
return 0;
}
int fpga_init() {
if(!fpgaInUse){
int fd;
int i = 0;
char buf[50];
int timeout = 10*1000; //10 sec
unsigned int stat;
// Allocate space for the fpga_dev
fpgaDev = malloc(sizeof(fpga_dev));
if (fpgaDev == NULL) {
fprintf(stderr, "Failed to malloc fpga_dev\n");
exit(EXIT_FAILURE);
//return -ENOMEM;
}
// Open the device file.
fd = open(FPGA_DEV_PATH, O_RDWR | O_SYNC);
if(fd < 0) {
return fd;
}
// Map the DMA regions.
for (i = NUM_CHANNEL-1; i >= 0; i--) {
fpgaDev->bufMem[i] = mmap(NULL, BUF_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, PCI_BAR_0_SIZE + (BUF_SIZE*i));
if(fpgaDev->bufMem[i] == MAP_FAILED)
break;
}
fpgaDev->numBuffers = NUM_CHANNEL-1 - i;
if(fpgaDev->numBuffers == 0)
exit(EXIT_FAILURE);
//return -ENOMEM;
// Map the config region.
fpgaDev->cfgMem = mmap(NULL, PCI_BAR_0_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, 0);
if(fpgaDev->cfgMem == MAP_FAILED) {
fprintf(stderr, "mmap() failed to map fpga config region\n");
exit(EXIT_FAILURE);
//return -ENOMEM;
}
// Initialize the channel fds
for (i = 0; i < NUM_CHANNEL; i++)
fpgaDev->intrFds[i] = -1;
for (i = 0; i < NUM_CHANNEL; i++){
fpga_channel_open(i,timeout);
}
//automatic exit function
fpgaInUse = true;
//Read the status register to get the link status
/*stat = fpga_reg_rd(STA_REG);
if(stat==0xFFFFFFFF){
printf("Fatal Error: The FPGA not detected by the host\n");
exit(EXIT_FAILURE);
}
if(!(stat&0x40000000))
printf("Fatal Error: The DRAM memory not detected by FPGA\n"); */
fprintf(stderr,"fpga initiated \n");
atexit(fpga_close);
return 0;
}
else{
fprintf(stderr,"FPGA is already in use\n");
return ERRINUSE;
}
}
