/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
// Set up Cortex_M3 or M4 VTOR register to point to vector table
SCB->VTOR = (unsigned int)&__Vectors;
fpuEnable();
// In case we are running from internal flash, we configure the flash
// accelerator.
#define FLASH_ACCELERATOR_SPEED 6
{
uint32_t *MAM, t;
// Set up flash controller for both banks
// Bank A
MAM = (uint32_t *)(LPC_CREG_BASE + 0x120);
t = *MAM;
t &= ~(0xF << 12);
*MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
// Bank B
MAM = (uint32_t *)(LPC_CREG_BASE + 0x124);
t = *MAM;
t &= ~(0xF << 12);
*MAM = t | (FLASH_ACCELERATOR_SPEED << 12);
}
board_init();
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if !defined(CORE_M0)
// Set up Cortex_M3 or M4 VTOR register to point to vector table
// This code uses a toolchain defined symbol to locate the vector table
// If this is not completed, interrupts are likely to cause an exception.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
*pSCB_VTOR = (unsigned int)&__vector_table;
#elif defined(__CODE_RED)
extern void *g_pfnVectors;
*pSCB_VTOR = (unsigned int)g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
*pSCB_VTOR = (unsigned int)&__Vectors;
#else
#error Unknown compiler
#endif
#else
// Cortex M0?
#error Cannot configure VTOR on Cortex_M0
#endif
#if defined(CORE_M4) && defined(USE_FPU)
fpuEnable();
#endif
// In case we are running from internal flash, we configure the flash
// accelerator. This is a conservative value that should work up to 204
// MHz on the LPC43xx or 180 MHz on the LPC18xx. This value may change
// as the chips are characterized and should also change based on
// core clock speed.
#define FLASH_ACCELERATOR_SPEED 6
#ifdef INTERNAL_FLASH
{
uint32_t *MAM,t;
// Set up flash controller for both banks
// Bank A
MAM = (uint32_t *)(LPC_CREG_BASE + 0x120);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
// Bank B
MAM = (uint32_t *)(LPC_CREG_BASE + 0x124);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
}
#endif
}
/*----------------------------------------------------------------------------*/
void platformStartup(void)
{
static const enum sysClockBranch blocksToDisable[] = {
CLK_APB3_I2C1,
CLK_APB3_DAC,
CLK_APB3_ADC0,
CLK_APB3_ADC1,
CLK_APB3_CAN0,
CLK_APB1_MCPWM,
CLK_APB1_I2C0,
CLK_APB1_I2S,
CLK_APB1_CAN1,
CLK_M4_SPIFI,
CLK_M4_LCD,
CLK_M4_ENET,
CLK_M4_USB0,
CLK_M4_EMC,
CLK_M4_SDIO,
CLK_M4_GPDMA,
CLK_M4_SCT,
CLK_M4_USB1,
CLK_M4_EMCDIV,
CLK_M4_M0APP,
CLK_M4_ADCHS,
CLK_M4_EEPROM,
CLK_M4_WWDT,
CLK_M4_USART0,
CLK_M4_UART1,
CLK_M4_SSP0,
CLK_M4_TIMER0,
CLK_M4_TIMER1,
CLK_M4_RIT,
CLK_M4_USART2,
CLK_M4_USART3,
CLK_M4_TIMER2,
CLK_M4_TIMER3,
CLK_M4_SSP1,
CLK_M4_QEI,
CLK_APB2_USART3,
CLK_APB2_USART2,
CLK_APB0_UART1,
CLK_APB0_USART0,
CLK_APB2_SSP1,
CLK_APB0_SSP0,
CLK_SPIFI,
CLK_SPI,
CLK_ADCHS,
CLK_AUDIO,
CLK_SDIO,
CLK_PERIPH_SGPIO
};
/*
* CLK_M4_BUS, CLK_M4_GPIO, CLK_M4_M4CORE, CLK_M4_FLASHA, CLK_M4_FLASHB,
* CLK_M4_SCU, CLK_M4_CREG are enabled by default.
* CLK_USB0, CLK_USB1, CLK_PERIPH_BUS, CLK_PERIPH_CORE are left untouched.
*/
for (unsigned int index = 0; index < ARRAY_SIZE(blocksToDisable); ++index)
sysClockDisable(blocksToDisable[index]);
#ifdef CONFIG_FPU
fpuEnable();
#endif
/* Reset SCU and GPIO blocks */
sysResetEnable(RST_SCU);
sysResetEnable(RST_GPIO);
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
uint32_t org;
#if !defined(__CODE_RED)
#if defined(CORE_M4) && defined(USE_FPU)
fpuEnable();
#endif
#endif
#if !defined(CORE_M0)
// Set up Cortex_M3 or M4 VTOR register to point to vector table
// This code uses a toolchain defined symbol to locate the vector table
// If this is not completed, interrupts are likely to cause an exception.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
org = *pSCB_VTOR = (unsigned int)&__vector_table;
#elif defined(__CODE_RED)
extern void *g_pfnVectors;
// CodeRed - correct to assign address of variable not contents
// org = *pSCB_VTOR = (unsigned int)g_pfnVectors;
org = *pSCB_VTOR = (unsigned int)&g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
org = *pSCB_VTOR = (unsigned int)&__Vectors;
#elif defined(__GNUC__)
extern void *__isr_vector;
org = *pSCB_VTOR = (unsigned int)&__isr_vector;
#else
#error Unknown compiler
#endif
#else
// Cortex M0?
#error Cannot configure VTOR on Cortex_M0
#endif
// LPC18xx/LPC43xx ROM sets the PLL to run from IRC and drive the part
// at 96 MHz out of reset
SystemCoreClock = 96000000;
// In case we are running from external flash, (booted by boot rom)
// We enable the EMC buffer to improve performance.
if(org == 0x1C000000)
{
/*Enable Buffer for External Flash*/
LPC_EMC->STATICCONFIG0 |= 1<<19;
}
// CodeRed - call clock init code by default
#ifdef __CODE_RED
// Call clock initialisation code
CGU_Init();
#endif
// In case we are running from internal flash, we configure the flash
// accelerator. This is a conservative value that should work up to 204
// MHz on the LPC43xx or 180 MHz on the LPC18xx. This value may change
// as the chips are characterized and should also change based on
// core clock speed.
#define FLASH_ACCELERATOR_SPEED 6
#ifdef INTERNAL_FLASH
{
uint32_t *MAM,t;
// Set up flash controller for both banks
// Bank A
MAM = (uint32_t *)(LPC_CREG_BASE + 0x120);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
// Bank B
MAM = (uint32_t *)(LPC_CREG_BASE + 0x124);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
}
#endif
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
uint32_t org;
#if defined(CORE_M4) && defined(USE_FPU)
fpuEnable();
#endif
#if !defined(CORE_M0)
// Set up Cortex_M3 or M4 VTOR register to point to vector table
// This code uses a toolchain defined symbol to locate the vector table
// If this is not completed, interrupts are likely to cause an exception.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
#if defined(__IAR_SYSTEMS_ICC__)
extern void *__vector_table;
org = *pSCB_VTOR = (unsigned int)&__vector_table;
#elif defined(__CODE_RED)
extern void *g_pfnVectors;
org = *pSCB_VTOR = (unsigned int)&g_pfnVectors;
#elif defined(__ARMCC_VERSION)
extern void *__Vectors;
org = *pSCB_VTOR = (unsigned int)&__Vectors;
#else
#error Unknown compiler
#endif
#else
// Cortex M0?
#error Cannot configure VTOR on Cortex_M0
#endif
// LPC18xx/LPC43xx ROM sets the PLL to run from IRC and drive the part
// at 96 MHz out of reset
SystemCoreClock = 96000000;
// In case we are running from internal flash, we configure the flash
// accelerator. This is a conservative value that should work up to 204
// MHz on the LPC43xx or 180 MHz on the LPC18xx. This value may change
// as the chips are characterized and should also change based on
// core clock speed.
#define FLASH_ACCELERATOR_SPEED 6
#ifdef INTERNAL_FLASH
{
volatile uint32_t *MAM;
uint32_t t;
// Set up flash controller for both banks
// Bank A
MAM = (volatile uint32_t *)(LPC_CREG_BASE + 0x120);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
// Bank B
MAM = (volatile uint32_t *)(LPC_CREG_BASE + 0x124);
t=*MAM;
t &= ~(0xF<<12);
*MAM = t | (FLASH_ACCELERATOR_SPEED<<12);
}
#endif
#ifdef EXTERNAL_PARALLEL_FLASH
// In case we are running from external flash, (booted by boot rom)
// We enable the EMC buffer to improve performance.
/*Enable Buffer for External Flash*/
// LPC_EMC->STATICCONFIG0 |= 1<<19;
// Also: We must enable address lines A14 and above. The boot rom only enables them to A13.
scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */
scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */
scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */
scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */
scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */
scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */
scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */
scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */
scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */
scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */
#endif
}
