void execute(treeNode *root){
tempClausesFileGlobal = NULL;
rootData *rdata = root->data;
compilerDebug(rdata);
postProc(rdata);
linkedList fullTransNodes = expandTrans(rdata);
indexList *varList = createVarList(rdata,fullTransNodes);
linkedList clauseList = createLinked(Malloc,Free);
clauseListGlobal = clauseList;
// don't need to create clauses if only getting final result
if(flagGlobal != FLAG_RESULT){
processAllClauses(rdata,varList,clauseList,fullTransNodes);
}
if(flagGlobal == FLAG_DEBUG){
printDebugClausesVars(DEBUG_CLAUSE_FILE,varList,clauseList);
}
if(flagGlobal == FLAG_CNF || flagGlobal == FLAG_DEBUG || flagGlobal == FLAG_RUN){
printClauses(CNF_FILE,varList,clauseList);
}
if(flagGlobal == FLAG_RUN){
runCnfSolver();
}
if(flagGlobal == FLAG_RESULT || flagGlobal == FLAG_RUN){
createSatOut(OUT_VARS_FILE,RESULT_FILE,rdata,varList,fullTransNodes);
}
if(flagGlobal != FLAG_RESULT){
deleteFile(TEMP_CLAUSE_FILE);
}
Free(sabrDirGlobal);
freeArch(root);
destroyLinked(fullTransNodes,singleFree);
destroyLinked(clauseList,singleFree);
destroyVarIndex(varList);
}
int
main(int argc,
char **argv)
{
int simSize = 14;
int xx;
simResults = (double *) malloc(simSize*sizeof(double));
simCounts = (unsigned long *) malloc(simSize*sizeof(unsigned long));
simIndex = 0;
for(xx = 0; xx < simSize ; xx++)
{
simResults[xx] = 0.0;
simCounts[xx] = 0;
}
t_options Options;
t_arch Arch = { 0 };
enum e_operation Operation;
struct s_placer_opts PlacerOpts;
struct s_annealing_sched AnnealSched;
struct s_router_opts RouterOpts;
struct s_det_routing_arch RoutingArch;
t_segment_inf *Segments;
t_timing_inf Timing;
t_subblock_data Subblocks;
boolean ShowGraphics;
boolean TimingEnabled;
int GraphPause;
/* Print title message */
PrintTitle();
/* Print usage message if no args */
if(argc < 2)
{
PrintUsage();
exit(1);
}
/* Read in available inputs */
ReadOptions(argc, argv, &Options);
/* Determine whether timing is on or off */
TimingEnabled = IsTimingEnabled(Options);
/* Use inputs to configure VPR */
SetupVPR(Options, TimingEnabled, &Arch, &Operation, &PlacerOpts,
&AnnealSched, &RouterOpts, &RoutingArch, &Segments,
&Timing, &Subblocks, &ShowGraphics, &GraphPause);
/* Check inputs are reasonable */
CheckOptions(Options, TimingEnabled);
CheckArch(Arch, TimingEnabled);
/* Verify settings don't conflict or otherwise not make sense */
CheckSetup(Operation, PlacerOpts, AnnealSched, RouterOpts,
RoutingArch, Segments, Timing, Subblocks, Arch.Chans);
/* Output the current settings to console. */
ShowSetup(Options, Arch, TimingEnabled, Operation, PlacerOpts,
AnnealSched, RouterOpts, RoutingArch, Segments, Timing,
Subblocks);
if(Operation == TIMING_ANALYSIS_ONLY) {
do_constant_net_delay_timing_analysis(
Timing, Subblocks, Options.constant_net_delay);
return 0;
}
/* Startup X graphics */
set_graphics_state(ShowGraphics, GraphPause, RouterOpts.route_type);
if(ShowGraphics)
{
init_graphics("VPR: Versatile Place and Route for FPGAs");
alloc_draw_structs();
}
/* Do the actual operation */
place_and_route(Operation, PlacerOpts, Options.PlaceFile,
Options.NetFile, Options.ArchFile, Options.RouteFile,
AnnealSched, RouterOpts, RoutingArch,
Segments, Timing, &Subblocks, Arch.Chans);
/* Close down X Display */
if(ShowGraphics)
close_graphics();
/* free data structures */
free(Options.PlaceFile);
free(Options.NetFile);
free(Options.ArchFile);
free(Options.RouteFile);
freeArch(&Arch);
printf("\nTiming Results\n");
for(xx = 0; xx < simSize ; xx++)
{
if(simCounts[xx] != 0)
{
simResults[xx] /= (double) simCounts[xx];
}
printf("Index: %d\tAverage Clock: %f\n", xx, simResults[xx]);
}
free(simResults);
free(simCounts);
/* Return 0 to single success to scripts */
return 0;
}
