int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; #ifndef CONFIG_USER_ONLY if (!is_a64(env)) { map_a32_to_a64_regs(env); } #endif if (n < 31) { /* Core integer register. */ return gdb_get_reg64(mem_buf, env->xregs[n]); } switch (n) { case 31: { unsigned int cur_el = arm_current_el(env); uint64_t sp; aarch64_save_sp(env, cur_el); switch (env->debug_ctx) { case DEBUG_EL0: sp = env->sp_el[0]; break; case DEBUG_EL1: sp = env->sp_el[1]; break; case DEBUG_EL2: sp = env->sp_el[2]; break; case DEBUG_EL3: sp = env->sp_el[3]; break; default: sp = env->xregs[31]; break; } return gdb_get_reg64(mem_buf, sp); } case 32: return gdb_get_reg64(mem_buf, env->pc); case 33: return gdb_get_reg32(mem_buf, pstate_read(env)); } /* Unknown register. */ return 0; }
static int cpu_read_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) { int ret; switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: ret = gdb_get_reg64(mem_buf, env->vregs[n][1].ll); break; case S390_V16_REGNUM ... S390_V31_REGNUM: ret = gdb_get_reg64(mem_buf, env->vregs[n][0].ll); ret += gdb_get_reg64(mem_buf + 8, env->vregs[n][1].ll); break; default: ret = 0; } return ret; }
int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int r = ppc_gdb_register_len_apple(n); if (!r) { return r; } if (n < 32) { /* gprs */ gdb_get_reg64(mem_buf, env->gpr[n]); } else if (n < 64) { /* fprs */ stfq_p(mem_buf, env->fpr[n-32]); } else if (n < 96) { /* Altivec */ stq_p(mem_buf, n - 64); stq_p(mem_buf + 8, 0); } else { switch (n) { case 64 + 32: gdb_get_reg64(mem_buf, env->nip); break; case 65 + 32: gdb_get_reg64(mem_buf, env->msr); break; case 66 + 32: { uint32_t cr = 0; int i; for (i = 0; i < 8; i++) { cr |= env->crf[i] << (32 - ((i + 1) * 4)); } gdb_get_reg32(mem_buf, cr); break; } case 67 + 32: gdb_get_reg64(mem_buf, env->lr); break; case 68 + 32: gdb_get_reg64(mem_buf, env->ctr); break; case 69 + 32: gdb_get_reg64(mem_buf, env->xer); break; case 70 + 32: gdb_get_reg64(mem_buf, env->fpscr); break; } } if (msr_le) { /* If cpu is in LE mode, convert memory contents to LE. */ ppc_gdb_swap_register(mem_buf, n, r); } return r; }
int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; if (n < 31) { /* Core integer register. */ return gdb_get_reg64(mem_buf, env->xregs[n]); } switch (n) { case 31: return gdb_get_reg64(mem_buf, env->xregs[31]); case 32: return gdb_get_reg64(mem_buf, env->pc); case 33: return gdb_get_reg32(mem_buf, pstate_read(env)); } /* Unknown register. */ return 0; }
static int cpu_read_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { switch (n) { case S390_FPC_REGNUM: return gdb_get_reg32(mem_buf, env->fpc); case S390_F0_REGNUM ... S390_F15_REGNUM: return gdb_get_reg64(mem_buf, get_freg(env, n - S390_F0_REGNUM)->ll); default: return 0; } }
int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; unsigned i; if (n < 0 || n >= env->config->gdb_regmap.num_regs) { return 0; } switch (reg->type) { case 9: /*pc*/ return gdb_get_reg32(mem_buf, env->pc); case 1: /*ar*/ xtensa_sync_phys_from_window(env); return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff) % env->config->nareg]); case 2: /*SR*/ return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]); case 3: /*UR*/ return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]); case 4: /*f*/ i = reg->targno & 0x0f; switch (reg->size) { case 4: return gdb_get_reg32(mem_buf, float32_val(env->fregs[i].f32[FP_F32_LOW])); case 8: return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64)); default: return 0; } case 8: /*a*/ return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]); default: qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n", __func__, n, reg->type); return 0; } }
int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; if (n < CPU_NB_REGS) { if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]); } else if (n < CPU_NB_REGS32) { return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]); } } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { #ifdef USE_X86LDOUBLE /* FIXME: byteswap float values - after fixing fpregs layout. */ memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10); #else memset(mem_buf, 0, 10); #endif return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; if (n < CPU_NB_REGS32 || (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); return 16; } } else { switch (n) { case IDX_IP_REG: if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { return gdb_get_reg64(mem_buf, env->eip); } else { return gdb_get_reg32(mem_buf, env->eip); } case IDX_FLAGS_REG: return gdb_get_reg32(mem_buf, env->eflags); case IDX_SEG_REGS: return gdb_get_reg32(mem_buf, env->segs[R_CS].selector); case IDX_SEG_REGS + 1: return gdb_get_reg32(mem_buf, env->segs[R_SS].selector); case IDX_SEG_REGS + 2: return gdb_get_reg32(mem_buf, env->segs[R_DS].selector); case IDX_SEG_REGS + 3: return gdb_get_reg32(mem_buf, env->segs[R_ES].selector); case IDX_SEG_REGS + 4: return gdb_get_reg32(mem_buf, env->segs[R_FS].selector); case IDX_SEG_REGS + 5: return gdb_get_reg32(mem_buf, env->segs[R_GS].selector); case IDX_FP_REGS + 8: return gdb_get_reg32(mem_buf, env->fpuc); case IDX_FP_REGS + 9: return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11); case IDX_FP_REGS + 10: return gdb_get_reg32(mem_buf, 0); /* ftag */ case IDX_FP_REGS + 11: return gdb_get_reg32(mem_buf, 0); /* fiseg */ case IDX_FP_REGS + 12: return gdb_get_reg32(mem_buf, 0); /* fioff */ case IDX_FP_REGS + 13: return gdb_get_reg32(mem_buf, 0); /* foseg */ case IDX_FP_REGS + 14: return gdb_get_reg32(mem_buf, 0); /* fooff */ case IDX_FP_REGS + 15: return gdb_get_reg32(mem_buf, 0); /* fop */ case IDX_MXCSR_REG: return gdb_get_reg32(mem_buf, env->mxcsr); } } return 0; }