void gen8_vec4_generator::generate_code(exec_list *instructions, struct annotation_info *annotation) { if (unlikely(debug_flag)) { if (shader_prog) { fprintf(stderr, "Native code for %s vertex shader %d:\n", shader_prog->Label ? shader_prog->Label : "unnamed", shader_prog->Name); } else { fprintf(stderr, "Native code for vertex program %d:\n", prog->Id); } } cfg_t *cfg = NULL; if (unlikely(debug_flag)) cfg = new(mem_ctx) cfg_t(instructions); foreach_list(node, instructions) { vec4_instruction *ir = (vec4_instruction *) node; struct brw_reg src[3], dst; if (unlikely(debug_flag)) annotate(brw, annotation, cfg, ir, next_inst_offset); for (unsigned int i = 0; i < 3; i++) { src[i] = ir->get_src(prog_data, i); } dst = ir->get_dst(); default_state.conditional_mod = ir->conditional_mod; default_state.predicate = ir->predicate; default_state.predicate_inverse = ir->predicate_inverse; default_state.saturate = ir->saturate; const unsigned pre_emit_nr_inst = nr_inst; generate_vec4_instruction(ir, dst, src); if (ir->no_dd_clear || ir->no_dd_check) { assert(nr_inst == pre_emit_nr_inst + 1 || !"no_dd_check or no_dd_clear set for IR emitting more " "than 1 instruction"); gen8_instruction *last = &store[pre_emit_nr_inst]; gen8_set_no_dd_clear(last, ir->no_dd_clear); gen8_set_no_dd_check(last, ir->no_dd_check); } }
void gen8_vec4_generator::generate_code(exec_list *instructions) { int last_native_inst_offset = 0; const char *last_annotation_string = NULL; const void *last_annotation_ir = NULL; if (unlikely(debug_flag)) { if (shader_prog) { printf("Native code for vertex shader %d:\n", shader_prog->Name); } else { printf("Native code for vertex program %d:\n", prog->Id); } } foreach_list(node, instructions) { vec4_instruction *ir = (vec4_instruction *) node; struct brw_reg src[3], dst; if (unlikely(debug_flag)) { if (last_annotation_ir != ir->ir) { last_annotation_ir = ir->ir; if (last_annotation_ir) { printf(" "); if (shader_prog) { ((ir_instruction *) last_annotation_ir)->print(); } else { const prog_instruction *vpi; vpi = (const prog_instruction *) ir->ir; printf("%d: ", (int)(vpi - prog->Instructions)); _mesa_fprint_instruction_opt(stdout, vpi, 0, PROG_PRINT_DEBUG, NULL); } printf("\n"); } } if (last_annotation_string != ir->annotation) { last_annotation_string = ir->annotation; if (last_annotation_string) printf(" %s\n", last_annotation_string); } } for (unsigned int i = 0; i < 3; i++) { src[i] = ir->get_src(prog_data, i); } dst = ir->get_dst(); default_state.conditional_mod = ir->conditional_mod; default_state.predicate = ir->predicate; default_state.predicate_inverse = ir->predicate_inverse; default_state.saturate = ir->saturate; const unsigned pre_emit_nr_inst = nr_inst; generate_vec4_instruction(ir, dst, src); if (ir->no_dd_clear || ir->no_dd_check) { assert(nr_inst == pre_emit_nr_inst + 1 || !"no_dd_check or no_dd_clear set for IR emitting more " "than 1 instruction"); gen8_instruction *last = &store[pre_emit_nr_inst]; gen8_set_no_dd_clear(last, ir->no_dd_clear); gen8_set_no_dd_check(last, ir->no_dd_check); } if (unlikely(debug_flag)) { disassemble(stdout, last_native_inst_offset, next_inst_offset); } last_native_inst_offset = next_inst_offset; }