void generic_timer_vcpu_context_restore(struct generic_timer_context *cntx) { generic_timer_reg_write64(GENERIC_TIMER_REG_VIRT_OFF, cntx->cntvoff); generic_timer_reg_write(GENERIC_TIMER_REG_KCTL, cntx->cntkctl); generic_timer_reg_write64(GENERIC_TIMER_REG_PHYS_CVAL, cntx->cntpcval); generic_timer_reg_write64(GENERIC_TIMER_REG_VIRT_CVAL, cntx->cntvcval); generic_timer_reg_write(GENERIC_TIMER_REG_PHYS_CTRL, cntx->cntpctl); generic_timer_reg_write(GENERIC_TIMER_REG_VIRT_CTRL, cntx->cntvctl); }
void generic_timer_vcpu_context_post_restore(void *vcpu_ptr, void *context) { u64 pcnt; struct vmm_vcpu *vcpu = vcpu_ptr; struct generic_timer_context *cntx = context; if (!cntx) { return; } pcnt = generic_timer_pcounter_read(); if ((cntx->cntpctl & GENERIC_TIMER_CTRL_ENABLE) && !(cntx->cntpctl & GENERIC_TIMER_CTRL_IT_MASK) && (cntx->cntpcval <= pcnt)) { cntx->cntpctl |= GENERIC_TIMER_CTRL_IT_MASK; generic_phys_irq_inject(vcpu, cntx); } if ((cntx->cntvctl & GENERIC_TIMER_CTRL_ENABLE) && !(cntx->cntvctl & GENERIC_TIMER_CTRL_IT_MASK) && ((cntx->cntvoff + cntx->cntvcval) <= pcnt)) { cntx->cntvctl |= GENERIC_TIMER_CTRL_IT_MASK; generic_virt_irq_inject(vcpu, cntx); } #ifdef HAVE_GENERIC_TIMER_REGS_RESTORE generic_timer_regs_restore(cntx); #else generic_timer_reg_write64(GENERIC_TIMER_REG_VIRT_OFF, cntx->cntvoff); generic_timer_reg_write(GENERIC_TIMER_REG_KCTL, cntx->cntkctl); generic_timer_reg_write64(GENERIC_TIMER_REG_PHYS_CVAL, cntx->cntpcval); generic_timer_reg_write64(GENERIC_TIMER_REG_VIRT_CVAL, cntx->cntvcval); generic_timer_reg_write(GENERIC_TIMER_REG_PHYS_CTRL, cntx->cntpctl); generic_timer_reg_write(GENERIC_TIMER_REG_VIRT_CTRL, cntx->cntvctl); #endif }