int nRF24L01P::write(int pipe, char *data, int count) {
// Note: the pipe number is ignored in a Transmit / write
//
// Save the CE state
//
int originalCe = ce_;
disable();
if ( count <= 0 ) return 0;
if ( count > _NRF24L01P_TX_FIFO_SIZE ) count = _NRF24L01P_TX_FIFO_SIZE;
// Clear the Status bit
setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
nCS_ = 0;
int status = spi_.write(_NRF24L01P_SPI_CMD_WR_TX_PAYLOAD);
for ( int i = 0; i < count; i++ ) {
spi_.write(*data++);
}
nCS_ = 1;
int originalMode = mode;
setTransmitMode();
enable();
wait_us(_NRF24L01P_TIMING_Thce_us);
disable();
while ( !( getStatusRegister() & _NRF24L01P_STATUS_TX_DS ) ) {
// Wait for the transfer to complete
}
// Clear the Status bit
setRegister(_NRF24L01P_REG_STATUS, _NRF24L01P_STATUS_TX_DS);
if ( originalMode == _NRF24L01P_MODE_RX ) {
setReceiveMode();
}
ce_ = originalCe;
wait_us( _NRF24L01P_TIMING_Tpece2csn_us );
return count;
}
mci::StatusRegister_t
Mci::sendCommand(mci::CommandWord_t cmdWord, mci::CommandArgument_t cmdArg)
{
#if defined(OS_DEBUG_AVR32_UC3_MCI_SENDCOMMAND)
OSDeviceDebug::putString("Mci cmd=");
OSDeviceDebug::putDec(cmdWord & 0x3F);
OSDeviceDebug::putString(", cmdWord=");
OSDeviceDebug::putHex(cmdWord);
OSDeviceDebug::putString(", arg=");
OSDeviceDebug::putHex(cmdArg);
OSDeviceDebug::putNewLine();
#endif /* defined(OS_DEBUG_AVR32_UC3_MCI_SENDCOMMAND) */
moduleRegisters.writeArgument(cmdArg);
moduleRegisters.writeCommand(cmdWord);
while (!isCommandReady())
; // TODO: reset WD
mci::StatusRegister_t ret;
ret = MCI_SUCCESS;
// Test error ==> if crc error and response R3 ==> don't check error
mci::StatusRegister_t status;
status = (getStatusRegister() & MCI_SR_ERROR);
if (status != 0)
{
// if the command is SEND_OP_COND the CRC error flag
// is always present (cf : R3 response)
if ((cmdWord == mci::CommandWord::SD_MMC_SDCARD_APP_OP_COND_CMD)
|| (cmdWord == mci::CommandWord::SD_MMC_MMC_SEND_OP_COND_CMD))
{
if ((status & AVR32_MCI_SR_RCRCE_MASK) == 0)
ret = status; // return only if not CRC
}
else
{
if ((status & AVR32_MCI_SR_RTOE_MASK) == 0)
// filter RTOE error which happens when using the HS mode
ret = status;
}
}
#if defined(OS_DEBUG_AVR32_UC3_MCI_SENDCOMMAND)
OSDeviceDebug::putString("Mci ret=");
OSDeviceDebug::putHex(ret);
OSDeviceDebug::putString(", stat=");
OSDeviceDebug::putHex(status);
OSDeviceDebug::putNewLine();
#endif /* defined(OS_DEBUG_AVR32_UC3_MCI_SENDCOMMAND) */
return ret;
}
bool
Mci::isCrcError(void)
{
if (getStatusRegister() & AVR32_MCI_SR_DCRCE_MASK)
{
// Clear the shadow bit
m_shadowStatusRegister &= ~AVR32_MCI_SR_DCRCE_MASK;
return true;
}
else
return false;
}
bool nRF24L01P::readable(int pipe) {
if ( ( pipe < NRF24L01P_PIPE_P0 ) || ( pipe > NRF24L01P_PIPE_P5 ) ) {
error( "nRF24L01P: Invalid readable pipe number %d\r\n", pipe );
return false;
}
int status = getStatusRegister();
return ( ( status & _NRF24L01P_STATUS_RX_DR ) && ( ( ( status & _NRF24L01P_STATUS_RX_P_NO ) >> 1 ) == ( pipe & 0x7 ) ) );
}
bool
Mci::isTxReady(void)
{
return (getStatusRegister() & AVR32_MCI_SR_TXRDY_MASK) != 0;
}
bool
Mci::isCommandReady(void)
{
return ((getStatusRegister() & AVR32_MCI_SR_CMDRDY_MASK) != 0);
}
bool
Mci::isTransferDone(void)
{
return ((getStatusRegister() & AVR32_MCI_SR_XFRDONE_MASK) != 0);
}
bool
Mci::isBusy(void)
{
return ((getStatusRegister() & AVR32_MCI_SR_NOTBUSY_MASK) == 0);
}
