C++ (Cpp) get_36x_per_dpll_param Examples

Example #1

File: clock.c Project: 5victor/u-boot-mini2440

static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
{
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	struct dpll_per_36x_param *ptr;

	ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();

	/* Moving it to the right sysclk base */
	ptr += clk_index;

	/* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
	sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
	wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);

	/* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
	sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);

	/* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
	sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);

	/* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
	sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);

	/* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
	sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);

	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
	sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);

	/* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
	sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);

	/* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
	sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);

	/* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
	sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);

	/* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
	sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
	wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}

Example #2

File: clock.c Project: RowanLiu/ported_uboot

static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
{
    struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
    struct dpll_per_36x_param *ptr;

    ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();

    /* Moving it to the right sysclk base */
    ptr += clk_index;

    /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
    wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);

    /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
    clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);

    /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
    clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);

    /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
    clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);

    /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
    clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);

    /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
    clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);

    /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
    clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);

    /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
    clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);

    /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
    clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);

    /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
    clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
    wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
}