/*!
* This is the probe routine for the DVFS driver.
*
* @param pdev The platform device structure
*
* @return The function returns 0 on success
*/
static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
{
int err = 0;
struct resource *res;
printk(KERN_INFO "mxc_dvfs_core_probe\n");
dvfs_dev = &pdev->dev;
dvfs_data = pdev->dev.platform_data;
INIT_DELAYED_WORK(&dvfs_core_handler, dvfs_core_work_handler);
pll1_sw_clk = clk_get(NULL, "pll1_sw_clk");
if (IS_ERR(pll1_sw_clk)) {
printk(KERN_INFO "%s: failed to get pll1_sw_clk\n", __func__);
return PTR_ERR(pll1_sw_clk);
}
cpu_clk = clk_get(NULL, dvfs_data->clk1_id);
if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
return PTR_ERR(cpu_clk);
}
dvfs_clk = clk_get(NULL, dvfs_data->clk2_id);
if (IS_ERR(dvfs_clk)) {
printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__);
return PTR_ERR(dvfs_clk);
}
core_regulator = regulator_get(NULL, dvfs_data->reg_id);
if (IS_ERR(core_regulator)) {
clk_put(cpu_clk);
clk_put(dvfs_clk);
printk(KERN_ERR "%s: failed to get gp regulator\n", __func__);
return PTR_ERR(core_regulator);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
err = -ENODEV;
goto err1;
}
dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
/*
* Request the DVFS interrupt
*/
dvfs_data->irq = platform_get_irq(pdev, 0);
if (dvfs_data->irq < 0) {
err = dvfs_data->irq;
goto err2;
}
/* request the DVFS interrupt */
err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs",
dvfs_dev);
if (err) {
printk(KERN_ERR
"DVFS: Unable to attach to DVFS interrupt,err = %d",
err);
goto err2;
}
clk_enable(dvfs_clk);
err = init_dvfs_controller();
if (err) {
printk(KERN_ERR "DVFS: Unable to initialize DVFS");
return err;
}
clk_disable(dvfs_clk);
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_enable.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
goto err3;
}
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
goto err3;
}
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_threshold.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
goto err3;
}
err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr);
if (err) {
printk(KERN_ERR
"DVFS: Unable to register sysdev entry for DVFS");
goto err3;
}
/* Set the current working point. */
cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
old_wp = 0;
curr_wp = 0;
dvfs_core_resume = 0;
#if defined(CONFIG_CPU_FREQ)
cpufreq_trig_needed = 0;
#endif
return err;
err3:
free_irq(dvfs_data->irq, dvfs_dev);
err2:
iounmap(dvfs_data->membase);
err1:
dev_err(&pdev->dev, "Failed to probe DVFS CORE\n");
return err;
}
/*!
* This is the probe routine for the bus frequency driver.
*
* @param pdev The platform device structure
*
* @return The function returns 0 on success
*
*/
static int __devinit busfreq_probe(struct platform_device *pdev)
{
int cpu_wp_nr;
main_bus_clk = clk_get(NULL, "main_bus_clk");
if (IS_ERR(main_bus_clk)) {
printk(KERN_DEBUG "%s: failed to get main_bus_clk\n", __func__);
return PTR_ERR(main_bus_clk);
}
pll2 = clk_get(NULL, "pll2");
if (IS_ERR(pll2)) {
printk(KERN_DEBUG "%s: failed to get pll2\n", __func__);
return PTR_ERR(pll2);
}
axi_a_clk = clk_get(NULL, "axi_a_clk");
if (IS_ERR(axi_a_clk)) {
printk(KERN_DEBUG "%s: failed to get axi_a_clk\n", __func__);
return PTR_ERR(axi_a_clk);
}
axi_b_clk = clk_get(NULL, "axi_b_clk");
if (IS_ERR(axi_b_clk)) {
printk(KERN_DEBUG "%s: failed to get axi_b_clk\n", __func__);
return PTR_ERR(axi_b_clk);
}
axi_c_clk = clk_get(NULL, "axi_c_clk");
if (IS_ERR(axi_c_clk)) {
printk(KERN_DEBUG "%s: failed to get axi_c_clk\n", __func__);
return PTR_ERR(axi_c_clk);
}
emi_core_clk = clk_get(NULL, "emi_core_clk");
if (IS_ERR(emi_core_clk)) {
printk(KERN_DEBUG "%s: failed to get emi_core_clk\n", __func__);
return PTR_ERR(emi_core_clk);
}
emi_intr_clk = clk_get(NULL, "emi_intr_clk");
if (IS_ERR(emi_intr_clk)) {
printk(KERN_DEBUG "%s: failed to get emi_intr_clk\n", __func__);
return PTR_ERR(emi_intr_clk);
}
nfc_clk = clk_get(NULL, "nfc_clk");
if (IS_ERR(nfc_clk)) {
printk(KERN_DEBUG "%s: failed to get nfc_clk\n", __func__);
return PTR_ERR(nfc_clk);
}
ahb_clk = clk_get(NULL, "ahb_clk");
if (IS_ERR(ahb_clk)) {
printk(KERN_DEBUG "%s: failed to get ahb_clk\n", __func__);
return PTR_ERR(ahb_clk);
}
vpu_core_clk = clk_get(NULL, "vpu_core_clk");
if (IS_ERR(vpu_core_clk)) {
printk(KERN_DEBUG "%s: failed to get vpu_core_clk\n", __func__);
return PTR_ERR(vpu_core_clk);
}
arm_axi_clk = clk_get(NULL, "arm_axi_clk");
if (IS_ERR(arm_axi_clk)) {
printk(KERN_DEBUG "%s: failed to get arm_axi_clk\n", __func__);
return PTR_ERR(arm_axi_clk);
}
ddr_clk = clk_get(NULL, "ddr_clk");
if (IS_ERR(ddr_clk)) {
printk(KERN_DEBUG "%s: failed to get ddr_clk\n", __func__);
return PTR_ERR(ddr_clk);
}
ipu_clk = clk_get(NULL, "ipu_clk");
if (IS_ERR(ipu_clk)) {
printk(KERN_DEBUG "%s: failed to get ipu_clk\n", __func__);
return PTR_ERR(ipu_clk);
}
vpu_clk = clk_get(NULL, "vpu_clk");
if (IS_ERR(vpu_clk)) {
printk(KERN_DEBUG "%s: failed to get vpu_clk\n", __func__);
return PTR_ERR(vpu_clk);
}
periph_apm_clk = clk_get(NULL, "periph_apm_clk");
if (IS_ERR(periph_apm_clk)) {
printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n",
__func__);
return PTR_ERR(periph_apm_clk);
}
lp_apm = clk_get(NULL, "lp_apm");
if (IS_ERR(lp_apm)) {
printk(KERN_DEBUG "%s: failed to get lp_apm\n", __func__);
return PTR_ERR(lp_apm);
}
cpu_clk = clk_get(NULL, "cpu_clk");
if (IS_ERR(cpu_clk)) {
printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__);
return PTR_ERR(cpu_clk);
}
osc = clk_get(NULL, "osc");
if (IS_ERR(osc)) {
printk(KERN_DEBUG "%s: failed to get osc\n", __func__);
return PTR_ERR(osc);
}
uart_clk = clk_get(NULL, "uart_clk.0");
if (IS_ERR(uart_clk)) {
printk(KERN_DEBUG "%s: failed to get uart_clk-0\n", __func__);
return PTR_ERR(uart_clk);
}
pll1 = clk_get(NULL, "pll1_sw_clk");
if (IS_ERR(pll1)) {
printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", __func__);
return PTR_ERR(pll1);
}
lp_regulator = regulator_get(NULL, lp_reg_id);
if (IS_ERR(lp_regulator)) {
clk_put(ahb_clk);
printk(KERN_DEBUG "%s: failed to get lp regulator\n", __func__);
return PTR_ERR(lp_regulator);
}
low_bus_freq_mode = 0;
high_bus_freq_mode = 1;
cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr);
return 0;
}
static int mc13892_reg_int(void)
{
int i = 0;
unsigned int value;
struct regulator *regulator;
struct cpu_wp *cpu_wp_tbl1;
int cpu_wp_nr1;
char *reg_name[] = {
"SW1",
"SW2",
"SW3",
"SW4",
"SW1_STBY",
"SW2_STBY",
"SW3_STBY",
"SW4_STBY",
"SW1_DVS",
"SW2_DVS",
"SWBST",
"VIOHI",
"VPLL",
"VDIG",
"VSD",
"VUSB2",
"VVIDEO",
"VAUDIO",
"VCAM",
"VGEN1",
"VGEN2",
"VGEN3",
"USB",
"GPO1",
"GPO2",
"GPO3",
"GPO4",
};
/* for board v1.1 do nothing */
if (!board_is_mx37(BOARD_REV_2))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(reg_name); i++) {
regulator = regulator_get(NULL, reg_name[i]);
if (regulator != ERR_PTR(-ENOENT)) {
regulator_enable(regulator);
regulator_put(regulator);
}
}
for (i = 0; i < ARRAY_SIZE(reg_name); i++) {
if ((strcmp(reg_name[i], "VIOHI") == 0) ||
(strcmp(reg_name[i], "VPLL") == 0) ||
(strcmp(reg_name[i], "VDIG") == 0) ||
(strcmp(reg_name[i], "VGEN2") == 0))
continue;
regulator = regulator_get(NULL, reg_name[i]);
if (regulator != ERR_PTR(-ENOENT)) {
regulator_disable(regulator);
regulator_put(regulator);
}
}
/* Set the current working point. */
cpu_wp_tbl1 = get_cpu_wp(&cpu_wp_nr1);
for (i = 0; i < cpu_wp_nr1; i++)
cpu_wp_tbl1[i].cpu_voltage += 50000;
/* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */
pmic_read_reg(REG_POWER_CTL0, &value, 0xffffff);
value |= 0x000010;
pmic_write_reg(REG_POWER_CTL0, value, 0xffffff);
return 0;
}
void init_ddr_settings(void)
{
unsigned long iram_paddr;
unsigned int reg;
int i;
struct cpu_wp *cpu_wp_tbl;
struct clk *ddr_clk = clk_get(NULL, "ddr_clk");
cpu_wp_tbl = get_cpu_wp(&i);
pll_rate = cpu_wp_tbl[0].pll_rate;
databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K);
/* Find the memory type, LPDDR2 or mddr. */
mx50_ddr_type = __raw_readl(databahn_base) & 0xF00;
if (mx50_ddr_type == MX50_LPDDR2) {
normal_databahn_settings = lpddr2_databhan_regs_offsets;
ddr_settings_size = ARRAY_SIZE(lpddr2_databhan_regs_offsets);
}
else if (mx50_ddr_type == MX50_MDDR) {
normal_databahn_settings = mddr_databhan_regs_offsets;
ddr_settings_size = ARRAY_SIZE(mddr_databhan_regs_offsets);
} else {
printk(KERN_DEBUG
"%s: Unsupported memory type\n", __func__);
return;
}
/* Copy the databhan settings into the iram location. */
for (i = 0; i < ddr_settings_size; i++) {
normal_databahn_settings[i][1] =
__raw_readl(databahn_base
+ normal_databahn_settings[i][0]);
}
/* Store the size of the array in iRAM also,
* increase the size by 8 bytes.
*/
iram_ddr_settings = iram_alloc((ddr_settings_size+1)*8, &iram_paddr);
if (iram_ddr_settings == NULL) {
printk(KERN_DEBUG
"%s: failed to allocate iRAM memory for ddr settings\n",
__func__);
return;
}
/* Allocate IRAM for the DDR freq change code. */
iram_alloc(SZ_8K, &iram_paddr);
/* Need to remap the area here since we want the memory region
to be executable. */
ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
SZ_8K, MT_HIGH_VECTORS);
memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K);
change_ddr_freq = (void *)ddr_freq_change_iram_base;
qosc_base = ioremap(QOSC_BASE_ADDR, SZ_4K);
/* Enable the QoSC */
reg = __raw_readl(qosc_base);
reg &= ~0xC0000000;
__raw_writel(reg, qosc_base);
/* Allocate IRAM to run the WFI code from iram, since
* we can turn off the DDR clocks when ARM is in WFI.
*/
iram_alloc(SZ_4K, &iram_paddr);
/* Need to remap the area here since we want the memory region
to be executable. */
wait_in_iram_base = __arm_ioremap(iram_paddr,
SZ_4K, MT_HIGH_VECTORS);
memcpy(wait_in_iram_base, mx50_wait, SZ_4K);
wait_in_iram = (void *)wait_in_iram_base;
clk_enable(ddr_clk);
/* Set the DDR to enter automatic self-refresh. */
/* Set the DDR to automatically enter lower power mode 4. */
reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22);
reg &= ~LOWPOWER_AUTOENABLE_MASK;
reg |= 1 << 1;
__raw_writel(reg, databahn_base + DATABAHN_CTL_REG22);
/* set the counter for entering mode 4. */
reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21);
reg &= ~LOWPOWER_EXTERNAL_CNT_MASK;
reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET;
__raw_writel(reg, databahn_base + DATABAHN_CTL_REG21);
/* Enable low power mode 4 */
reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20);
reg &= ~LOWPOWER_CONTROL_MASK;
reg |= 1 << 1;
__raw_writel(reg, databahn_base + DATABAHN_CTL_REG20);
clk_disable(ddr_clk);
epdc_clk = clk_get(NULL, "epdc_axi");
if (IS_ERR(epdc_clk)) {
printk(KERN_DEBUG "%s: failed to get epdc_axi_clk\n",
__func__);
return;
}
}
